Semiconductor package
A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.
1. A semiconductor package comprising:
a package substrate;
an interposer located over an upper surface of the package substrate and electrically connected to the package substrate;
a logic chip located over an upper surface of the interposer and electrically connected to the interposer;
a memory chip located over the upper surface of the interposer and electrically connected to the interposer and to the logic chip; and
a heat sink in thermal contact with an upper surface of the logic chip to dissipate heat in the logic chip,
wherein the heat sink has an upper surface coplanar with an upper surface of the memory chip.
2. The semiconductor package of claim 1 , wherein the heat sink comprises a dummy chip.
3. The semiconductor package of claim 2 , wherein the dummy chip comprises silicon.
4. The semiconductor package of claim 1 , further comprising a heat-transferring adhesive interposed between the logic chip and the heat sink.
5. The semiconductor package of claim 1 , further comprising a main heat sink making thermal contact with an upper surface of the memory chip and an upper surface of the heat sink to dissipate heat in the memory chip and the heat sink.
6. The semiconductor package of claim 5 , further comprising a heat-transferring adhesive interposed between the main heat sink and the upper surface of the memory chip, and between the main heat sink and the upper surface of the heat sink.
7. The semiconductor package of claim 1 , wherein the memory chip has a thickness that is greater than a thickness of the logic chip and an upper surface that is higher than the upper surface of the logic chip.
8. The semiconductor package of claim 1 , wherein the memory chip comprises a plurality of memory chips surrounding the logic chip.
9. The semiconductor package of claim 8 , wherein at least one of the memory chips has a multi-chip structure including vertically stacked memory chips.
10. The semiconductor package of claim 1 , wherein the interposer comprises:
an insulating substrate;
a plurality of connecting vias vertically arranged in the insulating substrate and electrically connected with the package substrate; and
a plurality of conductive patterns arranged on an upper surface of the insulating substrate to electrically connect the memory chip with the logic chip.
11. The semiconductor package of claim 10 , further comprising conductive bumps located between the connecting vias and the memory chip, and between the connecting vias and the logic chip.
12. The semiconductor package of claim 10 , further comprising conductive bumps located between the connecting vias and the package substrate.
13. The semiconductor package of claim 1 , further comprising an encapsulating member arranged in a space between the interposer and the memory chip, a space between the memory chip and the logic chip, a space between the memory chip and the heat sink, and on an outer side surface of the memory chip.
14. The semiconductor package of claim 1 , further comprising external terminals mounted on a lower surface of the package substrate.
15. A semiconductor package comprising:
a package substrate;
an interposer located over an upper surface of the package substrate and electrically connected with the package substrate;
a logic chip located over an upper surface of the interposer and electrically connected with the interposer;
a memory chip located over the upper surface of the interposer and electrically connected with the interposer and the logic chip, the memory chip having an upper surface that is higher than an upper surface of the logic chip;
a heat sink making thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip, the heat sink having an upper surface that is coplanar with the upper surface of the memory chip; and
a main heat sink directly making thermal contact with the upper surfaces of the memory chip and the heat sink to dissipate heat in the memory chip and the heat sink.
16. The semiconductor package of claim 15 , further comprising a heat-transferring adhesive interposed between and directly contacting the main heat sink and the memory chip, and interposed between and directly contacting the main heat sink and the heat sink.
17. The semiconductor package of claim 15 , wherein the memory chip comprises a plurality of memory chips surrounding the logic chip.
18. The semiconductor package of claim 15 , wherein the interposer comprises:
an insulating substrate;
a plurality of connecting vias vertically arranged in the insulating substrate and electrically connected with the package substrate; and
a plurality of conductive patterns arranged on an upper surface of the insulating substrate to electrically connect the memory chip with the logic chip.
19. The semiconductor package of claim 15 , further comprising:
an encapsulating member arranged in a space between the interposer and the memory chip, a space between the memory chip and the logic chip, a space between the memory chip and the heat sink, and on an outer side surface of the memory chip; and
external terminals mounted on a lower surface of the package substrate.