Method of designing an integrated circuit and integrated circuit

1. A method comprising:

reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines;

placing the cell in a chip-level layout, wherein the chip-level layout comprises a plurality of power rails;

determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track; and

adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

2. The method of claim 1 , wherein the plurality of routing tracks extends in a first direction, and the adjusting the position of the cell comprises moving the cell in a second direction perpendicular to the first direction.

3. The method of claim 1 , wherein the reserving the routing track comprises reserving a set of routing tracks, and an interval between adjacent reserved routing tracks of the set of routing tracks is equal to a pitch between adjacent power rails of the plurality of power rails.

4. The method of claim 1 , wherein the reserving the routing track comprises reserving a set of routing tracks, and an interval between adjacent reserved routing tracks of the set of routing tracks is less than a pitch between adjacent power rails of the plurality of power rails.

5. The method of claim 1 , wherein the reserving the routing track comprises reserving a set of routing tracks, and an interval between adjacent reserved routing tracks of the set of routing tracks is equal to a pitch between adjacent power rails of the plurality of power rails divided by an integer greater than one.

6. The method of claim 1 , further comprising designing the cell, wherein the designing the cell comprises placing the elements within the cell and placing the signal lines on the plurality of routing tracks other than the reserved routing track.

7. The method of claim 1 , further comprising receiving the cell from an external source.

8. The method of claim 1 , further comprising:

determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track following adjusting the position of the cell.

9. The method of claim 8 , further comprising:

modifying a design of the cell in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one of the routing tracks other than the reserved routing track for the cell having the adjusted position.

10. A method comprising:

designing a cell, wherein the cell comprises:

a plurality of elements,

a plurality of signal lines,

a plurality of non-reserved routing tracks, wherein each of the plurality of signal lines is placed in at least one of the plurality of non-reserved routing tracks, and

a plurality of reserved routing tracks, wherein each of the plurality of reserved routing tracks is free of all of the plurality of signal lines, and there is an interval between adjacent reserved routing tracks of the plurality of reserved routing tracks;

placing the cell in a chip-level layout, wherein the chip-level layout comprises a plurality of power rails having a pitch, and the pitch is different from the interval;

determining whether any of the plurality of power rails overlaps with any of the plurality of non-reserved routing tracks; and

adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one non-reserved routing track of the plurality of non-reserved routing tracks.

11. The method of claim 10 , wherein placing the cell in the chip-level layout comprises placing the cell in direct contact with a second cell in the chip-level layout.

12. The method of claim 10 , wherein the designing of the cell comprises designing the cell to have the interval less than the pitch.

13. The method of claim 10 , wherein the designing of the cell comprises designing the cell to have the interval equal to the pitch divided by an integer greater than one.

14. The method of claim 10 , further comprising:

determining whether any of the plurality of power rails overlaps with any of the plurality of non-reserved routing tracks following adjusting the position of the cell.

15. The method of claim 14 , further comprising:

modifying the cell in response to a determination that any of the plurality of power rails overlaps with any of the plurality of non-reserved routing tracks following adjusting the position of the cell.

16. The method of claim 15 , wherein the modifying of the cell comprises decreasing the interval.

17. An integrated circuit comprising:

a plurality of cells, wherein a first cell of the plurality of cells directly contacts a second cell of the plurality of cells, and each cell of the plurality of cells comprises:

a plurality of signal lines;

a plurality of non-reserved routing tracks, wherein signal lines of the plurality of signal lines are arranged in non-reserved routing tracks of the plurality of non-reserved routing tracks; and

a plurality of reserved routing tracks, wherein each of the plurality of reserved routing tracks is free of all of the plurality of signal lines, and adjacent reserved routing tracks of the plurality of reserved routing tracks are separated by an interval; and

a plurality of power rails, wherein adjacent power rails of the plurality of power rails are separated by a pitch, and each power rail of the plurality of power rails extends along a corresponding reserved routing track of the plurality of reserved routing tracks.

18. The integrated circuit of claim 17 , wherein the interval is equal to the pitch.

19. The integrated circuit of claim 17 , wherein the interval is equal to the pitch divided by an integer greater than one.

20. The integrated circuit of claim 17 , wherein a space between a boundary of the first cell of the plurality of cells and a reserved routing track of the plurality of reserved routing tracks is free of each non-reserved routing track of the plurality of non-reserved routing tracks.