Metal filament ReRAM cell with current limiting during program and erase
A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.
1. A ReRAM memory cell for use in a memory array, the ReRAM memory cell comprising:
a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element and coupled to a row power line in a row of the memory array;
a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including an n-channel transistor coupled between the second terminal of the ReRAM element and a first column bit line in a column of the memory array, the n-channel transistor having a gate coupled to an n-word line in the row of the memory array; and
an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell, the erase circuit including a p-channel transistor coupled between the second terminal of the ReRAM element and a second column bit line in the column in the memory array, the p-channel transistor having a gate coupled to a p-word line in the row of the memory array.
2. A ReRAM memory cell for use in a memory array, the ReRAM memory cell comprising:
a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element;
a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including a p-channel programming transistor coupled between the first terminal of the ReRAM element and a first column bit line in a column of the memory array, the p-channel programming transistor having a gate coupled to a first p-word line in a row of the memory array, and an n-channel programming transistor coupled between the second terminal of the ReRAM element and a second column bit line in the column in the memory array, the n-channel programming transistor having a gate coupled to a first n-word line in the row of the memory array; and
an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell, the erase circuit including an n-channel erase transistor coupled between the first terminal of the ReRAM element and the second column bit line in the column in the memory array, the n-channel erase transistor having a gate coupled to a second n-word line in the row of the memory array, and a p-channel erase transistor coupled between the second terminal of the ReRAM element and the first column bit line in the column in the memory array, the p-channel erase transistor having a gate coupled to a second p-word line in the row of the memory array.
3. A ReRAM memory cell for use in a memory array, the ReRAM memory cell comprising:
a ReRAM element having a first terminal and a second terminal, the first terminal connected to an ion-source electrode in the ReRAM element;
a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, the programming circuit including series-connected first and second p-channel programming transistors coupled between the first terminal of the ReRAM element and a first column bit line in a column in the memory array, the first one of the series connected p-channel programming transistors having a gate coupled to a first word line in a row of the memory array, the second one of the series connected p-channel programming transistors having a gate coupled to a second word line in the row of the memory array, and series connected first and second n-channel programming transistors coupled between the second terminal of the ReRAM element and a second column bit line in the column in the memory array, the first one of the series connected n-channel programming transistors having a gate coupled to a third word line in the row of the memory array, the second one of the series connected n-channel programming transistors having a gate coupled to a fourth word line in the row of the memory array; and
an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell, the erase circuit including series-connected first and second n-channel erase transistors coupled between the first terminal of the ReRAM element and a third column bit line in the column in the memory array, the first one of the series connected n-channel erase transistors having a gate coupled to the first word line in the row of the memory array, the second one of the series connected n-channel erase transistors having a gate coupled to the second word line in the row of the memory array, and series-connected first and second p-channel erase transistors coupled between the second terminal of the ReRAM element and a fourth column bit line in the column in the memory array, the first one of the series connected p-channel erase transistors having a gate coupled to the third word line in the row of the memory array, the second one of the series connected p-channel erase transistors having a gate coupled to the fourth word line in the row of the memory array.
4. A method for operating a ReRAM memory cell, the method comprising:
providing a ReRAM memory cell having a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell including at least one transistor configured in common source mode, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell including at least one transistor configured in common source mode, the erase circuit path being different from the programming circuit path; and
applying an erase potential to the ReRAM memory cell through the erase circuit path to erase the ReRAM memory cell;
monitoring current drawn by the ReRAM memory cell while the erase potential is being applied; and
removing the erase potential from the ReRAM memory cell when the decrease in current drawn by the ReRAM memory cell is greater that a preselected current threshold.
5. The method of claim 4 wherein the preselected current threshold is about a 50% decrease from the initial value of erase current.
6. The method of claim 4 further comprising:
applying a programming potential to the ReRAM memory cell through the programming circuit path to program the ReRAM memory cell.
7. A method for operating a ReRAM memory cell, the method comprising:
applying an erase potential to the ReRAM memory cell for a nominal erase time;
removing the erase potential from the ReRAM memory cell;
measuring leakage current drawn by the ReRAM memory cell;
if the leakage current drawn by the ReRAM memory cell is less than a predetermined threshold, ending the method;
if the leakage current drawn by the ReRAM memory cell is greater than the predetermined threshold, reprogramming the ReRAM memory cell; and
after the reprogramming the ReRAM memory cell, again applying the erase potential to the ReRAM memory cell for the nominal erase time.
8. The method of claim 7 wherein the leakage current predetermined threshold is between about 100 nano-Amperes to 500 nano-Amperes.
9. The method of claim 7 further comprising marking the ReRAM cell as defective if the leakage current drawn by the ReRAM memory cell is greater than the predetermined threshold after reprogramming and erasing the ReRAM memory cell more than a predetermined number of times.
10. The method of claim 9 wherein the predetermined number of times is between about 10 times and about 25 times.
11. A method comprising:
providing a ReRAM memory cell having a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell including at least one programming transistor configured in common source mode, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell including at least one erase transistor configured in common source mode, the erase circuit path being different from the programming circuit path; and
applying an erase potential to the ReRAM memory cell through the erase circuit path to cause an erase current to flow through the ReRAM memory cell,
wherein the erase current has a magnitude of between about 30% and about 75% of a magnitude of a programming current used to program the ReRAM memory cell.