Semiconductor integrated circuit adapted to output pass/fail results of internal operations
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
1. A semiconductor memory device comprising:
a memory cell array including a plurality of pages of memory cells;
a latch circuit configured to latch one page of data read from one page of the memory cells; and
a cache circuit configured to hold the one page of data transferred from the latch circuit,
wherein
upon receipt of
a first command,
an address indicating N page among the pages,
a second command, and
a third command,
the semiconductor memory device outputs the N-th page data stored at the cache circuit while reading (N+1)-th page data from the memory cell array to the latch circuit, N being an integer larger than 1.
2. The semiconductor memory device according to claim 1 , wherein
the semiconductor memory device concurrently outputs first and second information to outside of the semiconductor memory device in a status read operation,
the first information is true ready/busy information, and
the second information is cache ready/busy information.
3. The semiconductor memory device according to claim 1 , wherein
the N-th page data and the (N+1)-th page data are read from an identical block, and
memory cells included in the block are concurrently erasable.
4. The semiconductor memory device according to claim 2 , wherein
the semiconductor memory device outputs the first information from a first I/O pad to outside of the semiconductor memory device, and outputs the second information from a second I/O pad to the outside of the semiconductor memory device.
5. The semiconductor memory device according to claim 1 , wherein
after the semiconductor memory device receives another third command, an operation of outputting, by the cache circuit, the (N+1)-th page data to outside of the semiconductor memory device is executable in parallel with and concurrently with an operation of reading (N+2)-th page data from the memory cell by the latch circuit.
6. The semiconductor memory device according to claim 1 , wherein the latch circuit includes two inverters.
7. The semiconductor memory device according to claim 6 , wherein the cache circuit includes two inverters.
8. The semiconductor memory device according to claim 1 , further comprising an output circuit coupled to the latch circuit via the cache circuit.
9. The semiconductor memory device according to claim 8 , wherein
the output circuit is coupled to an I/O pad, and
the semiconductor memory device outputs the N-th page of data to outside of the semiconductor memory device from the I/O pad.
10. The semiconductor memory device according to claim 8 , wherein the cache circuit is coupled between a bit line and the output circuit.
11. A semiconductor memory device comprising:
a memory cell array including a plurality of pages of memory cells;
a cache circuit configured to hold one page of data input from an I/O pad; and
a latch circuit configured to latch the one page of data transferred from the cache circuit and transfer the latched data to one page of the memory cells,
wherein
upon receipt of
a first command,
a first address,
N-th page data,
a second command,
a third command,
a second address,
(N+1)-th page data, and
a fourth command,
the semiconductor memory device receives the (N±1)-th page data at the cache circuit while performing an operation of applying a voltage to write the N-th data to the memory cell in a write operation,
the third command is identical to the first command,
the fourth command is different from the second command, and
the latch circuit ends programming after the semiconductor memory device receives the fourth command.
12. The semiconductor memory device according to claim 11 , wherein
the N-th data and the (N+1)-th data are transferred to an identical block, and
memory cells included in the block are concurrently erasable.
13. The semiconductor memory device according to claim 11 , wherein
the latch circuit includes two inverters.
14. The semiconductor memory device according to claim 13 , wherein
the cache circuit includes two inverters.
15. The semiconductor memory device according to claim 11 , further comprising
a data input/output buffer coupled to the latch circuit via the cache circuit.
16. The semiconductor memory device according to claim 15 , wherein
the data input/output buffer is coupled to the I/O pad.
17. The semiconductor memory device according to claim 15 , wherein
the cache circuit is coupled between a bit line and the data input/output buffer.