High electron mobility transistor and method of fabricating the same
An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. The gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covers the second III-V compound layer. At least one electrode is disposed on the insulating layer and contacts the insulating layer, wherein a voltage is applied to the electrode.
1. A high electron mobility transistor (HEMT), comprising:
a first III-V compound layer;
a second III-V compound layer disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other;
a source electrode and a drain electrode disposed on the second III-V compound layer;
a gate electrode disposed on the second III-V compound layer between the source electrode and the drain electrode;
an insulating layer disposed between the drain electrode and the gate electrode and covering the second III-V compound layer, wherein the insulating layer conformally covers the source electrode, the drain electrode and the gate electrode; and
at least one electrode disposed on the insulating layer and contacting the insulating layer, wherein a voltage is applied to the electrode.
2. The HEMT of claim 1 , wherein the first III-V compound layer is gallium nitride, and the second III-V compound layer comprises aluminum gallium nitride, indium aluminum nitride, aluminum indium gallium nitride or aluminum nitride.
3. The HEMT of claim 1 , wherein the drain electrode electrically connects to the electrode.
4. The HEMT of claim 1 , wherein a drain voltage is applied to the drain electrode, and the drain voltage is different from the voltage applied to the electrode.
5. The HEMT of claim 1 , wherein the voltage is applied to remove trapped electrons within the first III-V compound layer and within the second III-V compound layer.
6. The HEMT of claim 1 , further comprising:
a third III-V compound layer disposed on the second III-V compound layer, wherein the third III-V compound layer comprises the same material as the first III-V compound layer and P-type dopants, or the third III-V compound layer comprises the same material as the second III-V compound layer and P-type dopants, and the gate electrode contacts the third III-V compound layer.
7. The HEMT of claim 6 , wherein the third III-V compound layer is P-type gallium nitride or P-type aluminum indium gallium nitride.
8. The HEMT of claim 1 , further comprising:
a fluorine-containing region disposed within the second III-V compound layer, wherein the gate electrode covers the fluorine-containing region.
9. The HEMT of claim 1 , further comprising:
a recess disposed in the second III-V compound layer, wherein the gate electrode is disposed in the recess.
10. The HEMT of claim 1 , wherein the insulating layer comprises aluminum nitride, silicon nitride or aluminum oxide.
11. The HEMT of claim 1 , wherein the insulating layer comprises dopants which are positive ions.
12. The HEMT of claim 1 , wherein a vertical direction is perpendicular to a top surface of the second III-V compound layer, and the electrode and the drain electrode do not overlap each other along the vertical direction.
13. A method of fabricating a high electron mobility transistor (HEMT), comprising:
providing a first III-V compound layer;
forming a second III-V compound layer disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other;
forming a source electrode, a drain electrode and a gate electrode on the second III-V compound layer, wherein the gate electrode is between the source electrode and the drain electrode;
forming an insulating layer conformally covering and contacting the second III-V compound layer, the drain electrode, the source electrode and the gate electrode; and
after forming the insulating layer, forming at least one electrode on the insulating layer between the drain electron and the gate electrode, the electrode contacting the insulating layer, wherein a voltage is applied to the electrode.
14. The method of fabricating an HEMT of claim 13 , wherein the insulating layer comprises aluminum nitride, silicon nitride or aluminum oxide.
15. The method of fabricating an HEMT of claim 13 , wherein the insulating layer comprises dopants which are positive ions.
16. The method of fabricating an HEMT of claim 13 , wherein the drain electrode electrically connects to the electrode.
17. The method of fabricating an HEMT of claim 13 , wherein a drain voltage is applied to the drain electrode, and the drain voltage is different from the voltage applied to the electrode.
18. The method of fabricating an HEMT of claim 13 , wherein the voltage is applied to remove trapped electrons within the first III-V compound layer and within the second III-V compound layer.
19. The method of fabricating an HEMT of claim 13 , wherein a vertical direction is perpendicular to a top surface of the second III-V compound layer, and the electrode and the drain electrode do not overlap each other along the vertical direction.