Semiconductor memory device which stores plural data in a cell
A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k⇐n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i⇐k) threshold voltage.
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells arranged in a matrix, each of the memory cells being capable of storing data of n bits; and
a control circuit configured to control the memory cell array, wherein
the control circuit writes m-bit (m<n) data to a first memory cell,
the control circuit subsequently writes the m-bit (m<n) data to a second memory cell adjacent to the first memory cell, and
the control circuit subsequently writes, to the first memory cell, n-bit data formed of the m-bit data stored in the first memory cell and (n-m) bit data.
2. The semiconductor memory device according to claim 1 , wherein after the m-bit data is written to the second memory cell, the control circuit subsequently writes the m-bit data to a third memory cell adjacent to the second memory cell in a direction different from the first memory cell, and
the control circuit subsequently writes, to the second memory cell, the n-bit data formed of the m-bit data stored in the second memory cell and the (n-m) bit data.
3. The semiconductor memory device according to claim 1 , further comprising:
a first word line connected to the first memory cell; and
a second word line connected to the second memory cell,
wherein the first word line and the second word line are adjacent to each other.
4. The semiconductor memory device according to claim 2 , further comprising:
a first word line connected to the first memory cell;
a second word line connected to the second memory cell; and
a third word line connected to the third memory cell,
wherein the first word line and the second word line are adjacent to each other, and
the second word line and the third word line are adjacent to each other.
5. The semiconductor memory device according to claim 1 , wherein the memory cells constitute a NAND flash memory.