High electron mobility transistors and power amplifiers including said transistors having improved performance and reliability
A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
1. A GaN-based high electron mobility transistor (HEMT) device configured to operate for greater than 1000 hours in a high-temperature-reverse-bias (HTRB) operation at 84 V drain bias, wherein the GaN-based HEMT device comprises:
a channel layer and a barrier layer sequentially stacked on a substrate;
a source contact comprising a first ohmic portion on the barrier layer, wherein the source contact is shared between a first unit cell transistor and a second unit cell transistor; and
a via extending in the channel layer, the barrier layer, and the substrate to the first ohmic portion of the source contact, wherein the via is between the first unit cell transistor and the second unit cell transistor.
2. The GaN-based HEMT device of claim 1 , wherein, after operating the HTRB operation for 1000 hours a gate leakage of the HEMT device is between 1×10 −4 and 1×10 −3 A.
3. The GaN-based HEMT device of claim 1 , wherein the HTRB operation is operated with a temperature of 150° C.
4. The GaN-based HEMT device of claim 1 , further comprising a gate contact on the barrier layer,
wherein the gate contact comprises a first portion and a second portion on the first portion, and
wherein the second portion extends beyond one or more sidewalls of the first portion.
5. The GaN-based HEMT device of claim 4 , wherein the second portion of the gate contact extends beyond a sidewall of the first portion of the gate contact towards the source contact by a distance that is between 0.5 μm and 0.15 μm.
6. A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device configured to operate for greater than 1000 hours in a high-temperature-reverse-bias (HTRB) operation at 84 V drain bias, wherein the GaN-based HEMT device comprises:
a channel layer and a barrier layer sequentially stacked on a substrate;
a source contact comprising a first ohmic portion on the barrier layer; and
a via extending in the channel layer, the barrier layer, and the substrate to the first ohmic portion of the source contact, wherein a width of the via decreases as the via extends from a bottom surface of the substrate to a top surface of the substrate.
7. The power amplifier of claim 6 , wherein the via has first and second opposing sidewalls,
wherein the first sidewall of the via is adjacent an active region of a first unit cell transistor of the GaN-based HEMT device, and
wherein the second sidewall of the via is adjacent an active region of a second unit cell transistor of the GaN-based HEMT device.
8. The power amplifier of claim 6 , wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at an output power at 1 dB compression (P1dB) during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
9. The power amplifier of claim 6 , wherein the P1dB value of the power amplifier is within 1 dB of maximum measured power during operation of the power amplifier between 26 GHz and 30.5 GHz.
10. The power amplifier of claim 6 , wherein, after operating the HTRB operation for 1000 hours a gate leakage of the HEMT device is between 1×10 −4 and 1×10 −3 A.
11. The power amplifier of claim 6 , wherein the HTRB operation is operated with a temperature of 150° C.
12. The power amplifier of claim 6 , further comprising a gate contact on the barrier layer,
wherein the gate contact comprises a first portion and a second portion on the first portion, and
wherein the second portion extends beyond one or more sidewalls of the first portion.
13. The power amplifier of claim 12 , further comprising a drain contact on the barrier layer, and
wherein the second portion of the gate contact extends beyond a sidewall of the first portion of the gate contact towards the drain contact by a distance that is between 0.5 μm and 0.15 μm.
14. The power amplifier of claim 12 , wherein the second portion of the gate contact extends beyond a sidewall of the first portion of the gate contact towards the source contact by a distance that is between 0.5 μm and 0.15 μm.
15. A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at an output power at 1 dB compression (P1dB) during operation of the power amplifier between 26.5 GHz and 30.5 GHz, wherein the GaN-based HEMT device comprises:
a channel layer and a barrier layer, sequentially stacked on a substrate;
a source contact comprising a first ohmic portion on the barrier layer; and
a via extending in the channel layer, the barrier layer, and the substrate to the first ohmic portion of the source contact, the via extending between active regions of two adjacent unit cell transistors of the GaN-based HEMT device.
16. The power amplifier of claim 15 , wherein the P1dB value of the power amplifier is within 1 dB of maximum measured power during operation of the power amplifier between 26 GHz and 30.5 GHz.
17. The power amplifier of claim 15 , wherein the power amplifier is configured to generate a power density greater than 3.5 W/mm while operating at 30 GHz.
18. The power amplifier of claim 15 , wherein a ratio of quiescent drain current to power output is approximately 12.5 mA/W or less.
19. The power amplifier of claim 15 , further comprising a first stage configured to provide gain compression and a second stage configured to provide gain expansion.
20. The power amplifier of claim 19 , wherein the first stage is biased in class A mode, and
wherein the second stage is biased in class AB mode.
21. The power amplifier of claim 20 , wherein a drive ratio between the first stage and the second stage is approximately 1:2.