Vertically stacked nFET and pFET with dual work function
A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.
1. A semiconductor structure comprising:
a pFET device comprising a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets; and
an nFET device stacked vertically above the pFET device and comprising a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets, wherein a seam is present between each Si channel material nanosheet of the first set of vertically stacked and suspended Si channel material nanosheets, and the seam is surrounded by the p-type work function metal.
2. The semiconductor structure of claim 1 , further comprising pFET S/D regions present on physically exposed sidewalls of each Si channel material nanosheet of the first set of vertically stacked and suspended Si channel material nanosheets, and nFET S/D regions present on physically exposed sidewalls of each Si channel material nanosheet of the second set of vertically stacked and suspended Si channel material nanosheets.
3. The semiconductor structure of claim 2 , further comprising a dielectric material located between each pFET S/D region and each nFET S/D region.
4. The semiconductor structure of claim 2 , further comprising a shared S/D contact structure located on a first side of the vertically stacked nFET and pFET devices.
5. The semiconductor structure of claim 4 , wherein the shared contact structure passes through one of the nFET S/D regions and into one of the underlying pFET S/D regions.
6. The semiconductor structure of claim 1 , wherein the p-type work function metal comprises TiN.
7. The semiconductor structure of claim 1 , further comprising a dielectric isolation layer located beneath the pFET device, the dielectric isolation layer is located on a surface of a semiconductor substrate.
8. The semiconductor structure of claim 1 , further comprising a metallic structure located above a topmost Si channel material nanosheet of the second set of vertically stacked and suspended Si channel material nanosheets.
9. The semiconductor structure of claim 8 , wherein the metallic structure is composed of a metal or metal alloy having a lower resistivity than the n-type work function metal.
10. The semiconductor structure of claim 9 , wherein the n-type work function metal includes a stack of TiN/Al-containing alloy/TiN, and the metallic structure is composed of tungsten or cobalt.
11. The semiconductor structure of claim 1 , wherein the first and second functional gate structures comprise a gate dielectric material, wherein the gate dielectric material of the first functional gate structure surrounds the p-type work function metal and wherein the gate dielectric material of the second functional gate structure surrounds the n-type work function metal.
12. The semiconductor structure of claim 1 , wherein the p-type work function metal comprises a metal nitride stack of atomic layer deposited TiN and chemical vapor deposited TiN.
13. The semiconductor structure of claim 12 , wherein the chemical vapor deposited TiN encapsulates each Si channel material nanosheet of the first set of vertically stacked and suspended Si channel material nanosheets.
14. The semiconductor structure of claim 1 , further comprising an inner spacer located between end segments of each Si channel material nanosheet of the first and second sets of vertically stacked and suspended Si channel material nanosheets.
15. The semiconductor structure of claim 14 , wherein the inner spacer has an outermost sidewalls that is vertically aligned to an outermost sidewall of each Si channel material nanosheet of the first and second sets of vertically stacked and suspended Si channel material nanosheets.
16. The semiconductor structure of claim 1 , wherein each Si channel material nanosheet of the first and second sets of vertically stacked and suspended Si channel material nanosheets is composed of unalloyed silicon.
17. The semiconductor structure of claim 1 , wherein the n-type work function metal is composed of hafnium, zirconium, titanium, tantalum, or aluminum, a metal carbide, an aluminide or any combination thereof.