Granted Patent B2

US 11,069,411 · App. 16/574,059 · Granted Jul 20, 2021

Abstract

Claims (15)

1. A programming circuit for use in a memory device, comprising:

a current source;

a transistor;

a capacitor coupled to a gate of the transistor;

a memory cell replica coupled to the current source;

a first switch for connecting the current source to the capacitor when the first switch is closed; and

a second switch for connecting the memory cell replica to the transistor when the second switch is closed;

wherein the transistor is capable of being coupled to a bit line to program a memory cell when the first switch is open and the second switch is open.

2. The circuit of claim 1 , wherein the transistor is an NMOS transistor.

3. A method for programming a memory cell, comprising:

coupling a current source to a capacitor through a first switch;

coupling a replica memory cell to a transistor through a second switch;

providing charge from the capacitor to a gate of the transistor; and

programming the memory cell using the transistor.

4. The method of claim 3 , wherein the transistor is an NMOS transistor.

Assignments (12)