Method of making split gate non-volatile flash memory cell
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
1. A method of forming a non-volatile memory cell comprising:
providing a semiconductor substrate having a memory cell region and a logic circuit region;
forming a pair of conductive floating gates disposed over and insulated from the memory cell region of the substrate;
forming a first source region in the substrate between the pair of floating gates;
forming a polysilicon layer over and insulated from the substrate in the memory cell region and the logic circuit region, wherein the polysilicon layer extends up and over, and is insulated from, the pair of conductive floating gates;
performing a first polysilicon etch to remove portions of the polysilicon layer such that a first block of the polysilicon layer between the floating gates and over the first source region is separated from remaining portions of the polysilicon layer;
forming an oxide layer over the substrate in the memory cell region and the logic circuit region;
forming a first block of photoresist on the polysilicon layer in a first portion of the logic circuit region;
performing an oxide etch to remove portions of the oxide layer except for at least spacers of the oxide layer in the memory cell region and a block of the oxide layer underneath the first block of photoresist;
forming a second block of photoresist on the polysilicon layer in a second portion of the logic circuit region;
performing a second polysilicon etch to remove portions of the polysilicon layer to result in:
a second block of the polysilicon layer disposed under one of the oxide spacers and over the substrate with one of the pair of floating gates disposed between the first and second blocks of the polysilicon layer,
a third block of the polysilicon layer disposed under one of the oxide spacers and over the substrate with the other of the pair of floating gates disposed between the first and third blocks of the polysilicon layer,
a fourth block of the polysilicon layer disposed under the block of the oxide layer in the first portion of the logic circuit region, and
a fifth block of the polysilicon layer disposed under the second block photoresist in the second portion of the logic circuit region;
forming a first drain region in the substrate adjacent a side of the second block of the polysilicon layer;
forming a second drain region in the substrate adjacent a side of the third block of the polysilicon layer;
forming a third drain region in the substrate adjacent a first side of the fourth block of the polysilicon layer;
forming a second source region in the substrate adjacent a second side of the fourth block of the polysilicon layer opposite the first side of the fourth block;
forming a fourth drain region in the substrate adjacent a first side of the fifth block of the polysilicon layer; and
forming a third source region in the substrate adjacent a second side of the fifth block of the polysilicon layer opposite the first side of the fifth block.
2. The method of claim 1 , further comprising:
forming a pair of conductive control gates each disposed over and insulated from one of the floating gates.