Precision tuning for the programming of analog neural memory in a deep learning artificial neural network
Numerous embodiments of a precision tuning algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
1. A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, the selected non-volatile memory cell comprising a floating gate and a control gate, the method comprising:
performing a coarse programming process comprising:
programming the non-volatile memory cell with an initial programming voltage;
applying a first voltage to the control gate of the selected non-volatile memory cell and measuring a first current that results through the selected non-volatile memory cell;
applying a second voltage to the control gate of the selected non-volatile memory cell and measuring a second current that results through the selected non-volatile memory cell;
determining a slope value based on the first voltage, the second voltage, the first current, and the second current;
determining a next programming voltage based on the slope value;
programming the non-volatile memory cell with the next programming voltage;
repeating the steps of determining a next programming voltage and programming the non-volatile memory cell with the next programming voltage until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value; and
performing a precision programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.
2. The method of claim 1 , wherein the step of performing a coarse programming process further comprises:
when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the coarse programming process.
3. The method of claim 1 , further comprising:
performing a second precision programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.
4. The method of claim 1 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
5. The method of claim 1 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
6. The method of claim 1 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
7. The method of claim 1 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog memory deep neural network.
8. The method of claim 1 , further comprising:
before performing the coarse programming process:
programming the selected non-volatile memory cell to a ‘0’ state; and
erasing the selected non-volatile memory cell to a weakly-erased level.
9. The method of claim 1 , further comprising:
before performing the coarse programming process:
erasing the selected non-volatile memory cell to a ‘1’ state; and
programming the selected non-volatile memory cell to a weakly-programmed level.
10. The method of claim 1 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
integrating the current drawn by the selected non-volatile memory cell during the read operation using an integrating analog-to-digital converter to generate digital bits.
11. The method of claim 1 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using a sigma delta analog-to-digital converter.
12. The method of claim 1 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using an algorithmic analog-to-digital.
13. The method of claim 2 , further comprising:
performing a second precision programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.
14. The method of claim 2 , wherein the precision programming process comprises applying voltage pulses of increasing magnitude to the control gate of the selected non-volatile memory cell.
15. The method of claim 2 , wherein the precision programming process comprises applying voltage pulses of increasing duration to the control gate of the selected non-volatile memory cell.
16. The method of claim 2 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
17. The method of claim 2 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog memory deep neural network.
18. The method of claim 2 , further comprising:
before performing the coarse programming process:
programming the selected non-volatile memory cell to a ‘0’ state; and
erasing the selected non-volatile memory cell to a weakly-erased level.
19. The method of claim 2 , further comprising:
before performing the coarse programming process:
erasing the selected non-volatile memory cell to a ‘1’ state; and
programming the selected non-volatile memory cell to a weakly-programmed level.
20. The method of claim 2 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
integrating the current drawn by the selected non-volatile memory cell during the read operation using an integrating analog-to-digital converter to generate digital bits.
21. The method of claim 2 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using a sigma delta analog-to-digital converter.
22. The method of claim 2 , further comprising:
performing a read operation on the selected non-volatile memory cell; and
converting the current drawn by the selected non-volatile memory cell during the read operation into digital bits using an algorithmic analog-to-digital converter.
23. The method of claim 1 , further comprising:
determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value by applying an input pulse to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current.
24. The method of claim 1 , further comprising:
determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value by applying a fixed bias to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current.
25. The method of claim 1 , further comprising:
determining if the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value by applying an input to a terminal of the non-volatile memory cell, modulating the current drawn by the selected non-volatile memory cell with an output pulse to generate a modulated output, digitizing the modulated output to generate digital output bits, and comparing the digital output bits to digital bits representing the first threshold current.