Transceiver and driver architecture with low emission and high interference tolerance
View Patent ↗Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.
1. Physical layer circuitry for interfacing with a communication bus of a wired local area network, the physical layer circuitry comprising:
a variable delay driver operably coupled to the communication bus, the communication bus comprising a shared transmission medium, the variable delay driver including:
a plurality of sub-drivers operably coupled in parallel between a driver input of the variable delay driver and a driver output of the variable delay driver, the variable delay driver configured to provide a driven transmit signal comprising a driven version of a transmit data signal at the driver output; and
one or more delay elements operably coupled between the driver input and one or more of the plurality of sub-drivers to deliver the transmit data signal to at least two of the sub-drivers at different points in time to control a slew rate of the driven transmit signal at the driver output.
2. The physical layer circuitry of claim 1 , wherein at least one of the plurality of sub-drivers includes an input stage and an intermediate stage.
3. The physical layer circuitry of claim 2 , wherein the input stage includes transistors that switch on and off faster than transistors of the intermediate stage.
4. The physical layer circuitry of claim 2 , wherein the intermediate stage includes transistors that tolerate higher voltage potential differences at their terminals than transistors of the input stage.
5. The physical layer circuitry of claim 1 , further comprising receiver circuitry operably coupled to the communication bus.
6. The physical layer circuitry of claim 5 , wherein the receiver circuitry includes detection circuitry.
7. The physical layer circuitry of claim 6 , wherein detection circuitry is configured to detect shorts, open circuits, or both in the communication bus.
8. The physical layer circuitry of claim 5 , wherein the receiver circuitry includes at least one receive amplifier.
9. The physical layer circuitry of claim 5 , further comprising a common mode dimmer configured to protect the receive circuitry from common mode interference.
10. The physical layer circuitry of claim 9 , wherein the common mode dimmer includes a differential amplifier operably coupled to a common mode dimmer cell, the differential amplifier configured drive the common mode dimmer cell to pull down common mode interference and pull up the common mode interference at the receiver circuitry.
11. The physical layer circuitry of claim 1 , further comprising a common mode choke operably coupled between the variable delay driver and the communication bus.
12. The physical layer circuitry of claim 1 , further comprising a Manchester encoder operably coupled to the driver input.
13. Circuitry of a physical layer for interfacing with a communication bus of a wired local area network, the circuitry comprising:
receiver circuitry operably coupled to the communication bus, the communication bus including a shared transmission medium; and
a common mode dimmer operably coupled to the receiver circuitry and the communication bus, the common mode dimmer configured to protect the receiver circuitry from common mode interference, the common mode dimmer comprising:
a differential amplifier; and
a common mode dimmer cell operably coupled to the differential amplifier.
14. The circuitry of claim 13 , wherein the communication bus is operably coupled to an inverting input of the differential amplifier.
15. The circuitry of claim 14 , wherein the communication bus is operably coupled to the inverting input of the differential amplifier through two pairs of resistors.
16. The circuitry of claim 13 , further comprising voltage reference circuitry operably coupled to a non-inverting input of the differential amplifier, the voltage reference circuitry configured to provide a reference voltage to the non-inverting input of the differential amplifier.
17. The circuitry of claim 16 , wherein the common mode dimmer is configured to maintain voltage levels at the receiver circuitry at or below the reference voltage.
18. The circuitry of claim 13 , wherein the common mode dimmer cell includes two pairs of transistors, each pair of the two pairs of transistors coupled in series between a first power rail voltage potential node and a second power rail voltage potential node, the first power rail voltage potential node higher than the second power rail voltage potential node, a first power rail voltage potential associated with the first power rail voltage potential node higher than a second power rail voltage potential associated with the second power rail voltage potential node.
19. The circuitry of claim 18 , wherein drains of a first pair of transistors of the two pairs of transistors are operably coupled to a first input terminal of the common mode dimmer and drains of a second pair of transistors of the two pairs of transistors are operably coupled to a second input terminal of the common mode dimmer.
20. The circuitry of claim 18 , wherein gates of N-type Metal Oxide Semiconductor transistors of the two pairs of transistors are operably coupled to an inverting output of the differential amplifier.
21. The circuitry of claim 18 , wherein gates of P-type Metal Oxide Semiconductor (PMOS) transistors of the two pairs of transistors are operably coupled to a gate of an other PMOS transistor, the other PMOS transistor operably coupled in series with an N-type Metal Oxide Semiconductor (NMOS) transistor between the first power rail voltage potential node and the second power rail voltage potential node, a gate of the NMOS transistor operably coupled to a non-inverting output of the differential amplifier.
22. The circuitry of claim 13 , further comprising transmit circuitry including a variable delay driver operably coupled to the communication bus.
23. The circuitry of claim 13 , further comprising one or more resistors coupled between the common mode dimmer and the communication bus.
24. Circuitry of a physical layer for interfacing with a communication bus of a wired local area network, the circuitry comprising:
a variable delay driver operably coupled to the communication bus comprising a shared transmission medium, the variable delay driver configured to control a slew rate of a driven transmit signal at a driver output;
receiver circuitry operably coupled to the communication bus; and
a common mode dimmer operably coupled to the receiver circuitry and the communication bus, the common mode dimmer configured to protect the receiver circuitry from common mode interference;
wherein:
the variable delay driver is further configured to control an amplitude of voltage signals at a driver output of the variable delay driver;
the variable delay driver includes a plurality of sub-drivers; and
at least one of the plurality of sub-drivers includes at least one variable current source configured to control an amount of current provided to the at least one of the plurality of sub-drivers, thereby controlling an amplitude of voltage signals at a driver output of the variable delay driver.
25. The circuitry of claim 24 , further comprising a common mode choke operably coupled between the communication bus and the variable delay driver, the common mode dimmer, and the receiver circuitry, the common mode choke configured to suppress the common mode interference on the communication bus.
26. The circuitry of claim 24 , further comprising a Manchester encoder operably coupled to a driver input of the variable delay driver.
27. The circuitry of claim 24 , further comprising one or more capacitors operably coupled between the communication bus and the variable delay driver, the receiver circuitry, and the common mode dimmer, the one or more capacitors configured to isolate the variable delay driver, the receiver circuitry, and the common mode dimmer from direct current voltages on the communication bus.