Switch control circuitry
Disclosed herein are silicon-on-insulator (SOI) switches and associated control circuits having level shifters configured to provide increased voltages (positive and/or negative) to the switches. The disclosed level shifters can be configured to provide increased voltages and can be used with high-linearity switches and/or can improve the linearity of switches. The improved switch performance can improve front end module performance for applications such as carrier aggregation (CA) and multiple input multiple output (MIMO) as well as with protocols such as Long-Term Evolution Advanced (or LTE-A).
1. A voltage level circuit comprising:
a first outer transistor stack including at least six transistors in series between a high voltage input port and a low voltage input port, with at least three series p-channel metal-oxide-semiconductor field effect (PMOS) transistors in series with at least three series n-channel metal-oxide-semiconductor field effect (NMOS) transistors;
a second outer transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the second outer transistor stack including at least six transistors in series with at least three series PMOS transistors in series with at least three series NMOS transistors;
a first inner transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the first inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors;
a second inner transistor stack coupled in parallel with the second outer transistor stack between the high voltage input port and the low voltage input port, the second inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors;
at least two inner PMOS transistors that are cross-coupled, a first inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the first inner transistor stack and a second inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the second inner transistor stack;
an input port configured to receive an input signal; and
an output port configured to provide an output signal such that in response to receiving a high signal at the input port the output port provides a voltage approximately equal to a voltage provided at the high voltage input port and in response to receiving a low signal at the input port the output port provides a voltage approximately equal to a voltage provided at the low voltage input port.
2. The circuit of claim 1 further comprising a complementary input port configured to receive a complement of the input signal.
3. The circuit of claim 1 wherein the output port is coupled between the three series PMOS transistors and the three series NMOS transistors of the first outer transistor stack.
4. The circuit of claim 1 further comprising a complementary output port configured to provide a second output signal.
5. The circuit of claim 4 wherein in response to receiving a high signal at the input port the complementary output port provides a voltage approximately equal to a voltage provided at the low voltage input port and in response to receiving a low signal at the input port the complementary output port provides a voltage approximately equal to a voltage provided at the high voltage input port.
6. The circuit of claim 4 wherein the complementary output port is coupled between the three series PMOS transistors and the three series NMOS transistors of the second outer transistor stack.
7. The circuit of claim 1 wherein a drain of an NMOS transistor coupled to the low voltage input port of the first inner transistor stack is coupled to a gate of an NMOS transistor coupled to the low voltage input port of the first outer transistor stack.
8. The circuit of claim 7 wherein a drain of an NMOS transistor coupled to the low voltage input port of the second inner transistor stack is coupled to a gate of an NMOS transistor coupled to the low voltage input port of the second outer transistor stack.
9. The circuit of claim 1 further comprising a first bias input configured to receive a first bias signal, a second bias input configured to receive a second bias signal, and a third bias input configured to receive a third bias signal.
10. The circuit of claim 9 wherein, in the first outer transistor stack, a gate of a first PMOS transistor that has its source coupled to the high voltage input port receives a complement of the input signal, a gate of a second PMOS transistor that has its source coupled to a drain of the first PMOS transistor receives the first bias signal, a gate of a third PMOS transistor that has its source coupled to a drain of the second PMOS transistor receives the second bias signal, a gate of a first NMOS transistor that has its drain coupled to a drain of the third PMOS transistor receives the second bias signal, and a gate of a second NMOS transistor that has its drain coupled to a source of the first NMOS transistor receives the third bias signal.
11. The circuit of claim 10 wherein, in the first inner transistor stack, a gate of a first PMOS transistor that has its source coupled to the high voltage input port receives the input signal, a gate of a second PMOS transistor that has its source coupled to a drain of the first PMOS transistor receives the first bias signal, a gate of a first NMOS transistor that has its drain coupled to a drain of the second PMOS transistor receives the second bias signal.
12. The circuit of claim 1 further comprising one or more diodes coupled between two of the NMOS series transistors of the first inner transistor stack.
13. A switch control circuit comprising one or more of the circuits of claim 1 wherein the switch control circuit is configured to generate a negative voltage of at least −4 V.
14. A radio-frequency (RF) module comprising:
a packaging substrate configured to receive a plurality of components; and
a switching circuit implemented on the packaging substrate, the switching circuit including a voltage level shifter having first outer transistor stack including at least six transistors in series between a high voltage input port and a low voltage input port, with at least three series p-channel metal-oxide-semiconductor field effect (PMOS) transistors in series with at least three series n-channel metal-oxide-semiconductor field effect (NMOS) transistors, the switching circuit further including a second outer transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the second outer transistor stack including at least six transistors in series with at least three series PMOS transistors in series with at least three series NMOS transistors, the voltage level shifter further including a first inner transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the first inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors, the voltage level shifter further including a second inner transistor stack coupled in parallel with the second outer transistor stack between the high voltage input port and the low voltage input port, the second inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors, the voltage level shifter further including at least two inner PMOS transistors that are cross-coupled, a first inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the first inner transistor stack and a second inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the second inner transistor stack, the voltage level shifter further including an input port configured to receive an input signal, the voltage level shifter further including an output port configured to provide an output signal such that in response to receiving a high signal at the input port the output port provides a voltage approximately equal to a voltage provided at the high voltage input port and in response to receiving a low signal at the input port the output port provides a voltage approximately equal to a voltage provided at the low voltage input port.
15. The RF module of claim 14 wherein the RF module is a front-end module.
16. The RF module of claim 14 wherein the switching circuit further comprises a voltage generator to output a positive voltage provided to the high voltage input port and a negative voltage provided to the low voltage input port.
17. The RF module of claim 16 wherein the switching circuit further includes a series arm configured to receive an RF signal and to output the RF signal in an on state, the series arm configured to receive the positive voltage through the voltage level shifter to put the series arm in the on state and to receive the negative voltage through the voltage level shifter to put the series arm in an off state.
18. The RF module of claim 17 wherein the switching circuit is implemented on a single semiconductor die.
19. A wireless device comprising:
a transceiver configured to generate a radio-frequency (RF) signal;
a front-end module (FEM) in communication with the transceiver, the FEM including a packaging substrate configured to receive a plurality of components, the FEM further including a switching circuit implemented on the packaging substrate, the switching circuit including a voltage level shifter having first outer transistor stack including at least six transistors in series between a high voltage input port and a low voltage input port, with at least three series p-channel metal-oxide-semiconductor field effect (PMOS) transistors in series with at least three series n-channel metal-oxide-semiconductor field effect (NMOS) transistors, the switching circuit further including a second outer transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the second outer transistor stack including at least six transistors in series with at least three series PMOS transistors in series with at least three series NMOS transistors, the voltage level shifter further including a first inner transistor stack coupled in parallel with the first outer transistor stack between the high voltage input port and the low voltage input port, the first inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors, the voltage level shifter further including a second inner transistor stack coupled in parallel with the second outer transistor stack between the high voltage input port and the low voltage input port, the second inner transistor stack including at least four transistors in series with at least two series PMOS transistors in series with at least two series NMOS transistors, the voltage level shifter further including at least two inner PMOS transistors that are cross-coupled, a first inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the first inner transistor stack and a second inner PMOS transistor having its source coupled to a gate of a PMOS transistor of the second inner transistor stack, the voltage level shifter further including an input port configured to receive an input signal, the voltage level shifter further including an output port configured to provide an output signal such that in response to receiving a high signal at the input port the output port provides a voltage approximately equal to a voltage provided at the high voltage input port and in response to receiving a low signal at the input port the output port provides a voltage approximately equal to a voltage provided at the low voltage input port; and
an antenna in communication with the FEM, the antenna configured to transmit the amplified RF signal.
20. The wireless device of claim 19 wherein the switching circuit comprises a dual pole dual throw switch configured to swap the RF signal between the antenna and a diversity antenna.