Stacked die semiconductor package spacer die
Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.
1. A semiconductor package comprising:
a substrate having an upper surface, a transversely opposed second surface, and a substrate footprint area and a contact pad array disposed on the second surface of the substrate;
wherein the contact pad array includes a plurality of contact pads arranged in a first pattern; and
wherein the first pattern includes a plurality of peripheral electrical contact pads and a plurality of mechanical contact pads;
a first die stack having a first die stack footprint area, the first die stack comprising a first die vertically over a second die, the first die having a footprint smaller than and entirely within a footprint of the second die, and the first die stack footprint area less than the substrate footprint area; and
a spacer die disposed between the upper surface of the substrate and first die stack the spacer die having a footprint area that is greater than the first die stack footprint area and the same or smaller than the substrate footprint area;
wherein the first die stack physically couples to the upper surface of the spacer die in a location such that the first die stack footprint area partially overlaps a portion of the plurality of peripheral electrical contact pads from a plan view perspective, wherein the plurality of mechanical contact pads is outside of the first die stack footprint area; and
wherein the spacer die footprint area completely overlaps the portion of the plurality of peripheral electrical contact pads at least partially overlapped by the first die stack footprint from the plan view perspective, wherein the spacer die footprint area overlaps the plurality of mechanical contact pads, and wherein there are no contact pads on the second surface of the substrate outside of the spacer die footprint area.
2. The semiconductor package of claim 1 , further comprising:
a plurality of solder balls, each of the plurality of solder balls conductively coupled to a respective one of the plurality of contact pads.
3. The semiconductor package of claim 1 , further comprising:
an encapsulant disposed about at least a portion of the first die stack.
4. The semiconductor package of claim 1 , further comprising:
a second die stack having a second die stack footprint area;
wherein a combined footprint area of the first die stack and the second die stack is less than the substrate footprint area;
wherein the first die stack and the second die stack footprint are spaced apart to provide an interstitial space between the first die stack footprint and the second die stack footprint;
wherein at least some of the plurality contact pads are disposed on the second surface of the substrate in the interstitial space between the first die stack footprint and the second die stack footprint such that the contact pads disposed in the interstitial space are partially overlapped from the plan view perspective by at least one of:
the first die stack footprint or the second die stack footprint;
wherein the spacer die is disposed between the upper surface of the substrate and the first and the second die stacks; and
wherein the spacer die footprint area completely overlaps the portion of the plurality of peripheral electrical contact pads at least partially overlapped by the first die stack footprint and the contact pads disposed in the interstitial space between the first die stack and the second die stack from the plan view perspective.
5. The semiconductor package of claim 4 :
wherein the second die stack communicably couples to the upper surface of the spacer die in a location such that the second die stack footprint partially overlaps a portion of the plurality of peripheral electrical contact pads from the plan view perspective;
wherein the spacer die footprint area completely overlaps the portion of the plurality of peripheral electrical contact pads at least partially overlapped by the footprint of the second die stack from the plan view perspective.
6. The semiconductor package of claim 4 wherein the first die stack and the second die stack comprise a system on a chip (SoC).
7. The semiconductor package of claim 1 wherein the spacer die comprises a silicon spacer die.
8. The semiconductor package of claim 7 wherein the silicon spacer die comprises a silicon-containing material having a thickness of from about 10 micrometers (μm) to 100 μm.
9. The semiconductor package of claim 1 , further comprising a die attach film disposed between the first die stack and the spacer die;
wherein the die attach film comprises a material having a first modulus of elasticity;
wherein the spacer die comprises a material having a second modulus of elasticity; and
wherein a difference between the first modulus of elasticity and the second modulus of elasticity is less than 10% of the larger of the first modulus of elasticity or the second modulus of elasticity.