IP Library Granted Patent US 11,431,468
Granted Patent B2
US 11,431,468 · App. 16/653,688 · Granted Aug 30, 2022

Physical layer to link layer interface and related systems, methods and devices

Inventors: Venkatraman Iyer (Austin, TX); Dixon Chen (Shenzhen, CN); John Junling Zang (Shenzhen, CN); Shivanand I. Akkihal (Austin, TX)
Assignee: Microchip Technology Incorporated
H04L7/0041H04L69/323
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,431,468
App. No.
16/653,688
Granted
Aug 30, 2022
Kind
B2
Abstract

Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Claims (23)

1. A method comprising: starting a data reception from a shared transmission medium; detecting a collision at the shared transmission medium; waiting to send receive data to a link layer until after a delay period at least partially responsive to detecting the collision; and after ending the data reception from the shared transmission medium, generating signaling for indicating that the shared transmission medium is active, wherein the generating the signaling for indicating that the shared transmission medium is active comprises: asserting, at an output, a first signal for a period equal to the delay period less a period corresponding to an inter-frame gap.

2. The method of claim 1 , wherein the output at which the first signal is asserted is assigned to exclusively signal carrier activity at the shared transmission medium.

3. The method of claim 1 , comprising: de-asserting, at the output, the first signal for a period equal to the inter-frame gap.

4. The method of claim 3 , comprising: finishing providing delayed receive data to an output for sending receive data to the link layer after the first signal is de-asserted.

5. The method of claim 1 , wherein the output at which the first signal is asserted is assigned to exclusively signal carrier activity at the shared transmission medium.

6. The method of claim 1 , comprising: de-asserting, at the output, the first signal for a period equal to an inter-frame gap.

7. The method of claim 1 , wherein the waiting to send receive data to the link layer until after the delay period comprises: waiting to send the receive data to the link layer until after a uniform delay period.

8. A system, comprising: an interface to operatively couple a physical layer side of the system and a link layer side of the system; a receive datapath to move receive data at the physical layer side of the system toward the link layer side of the system, the moving the receive data comprising: starting a data reception from a shared transmission medium;

and delaying at least some of the moving of the receive data until after a delay period at least partially responsive to detection of a collision at the shared transmission medium, and a tuning circuitry of the physical layer side, the tuning circuitry to, after an end of the data reception from the shared transmission medium, generate signaling for indicating that the shared transmission medium is active at least partially by asserting, at an output of the interface, a first signal for a period equal to the delay period less a period corresponding to an inter-frame gap.

9. The system of claim 8 , wherein the receive datapath comprises sensing circuitry to provide a collision signal indicative of a collision at the shared transmission medium, and wherein the receive datapath is to delay some of the moving of the receive data until after the delay period responsive to the collision signal.

10. The system of claim 8 , wherein the output of the interface at which the first signal is asserted is for exclusively signaling carrier activity at the shared transmission medium.

11. The system of claim 8 , wherein the period of the first signal is chosen to end before the receive datapath finishes sending delayed receive data.

12. The system of claim 8 , wherein the tuning circuitry is to generate the signaling for indicating that the shared transmission is active by: de-asserting, at the output, the first signal for a period equal to an inter-frame gap.

13. The system of claim 8 , wherein the tuning circuitry is to generate the signaling for indicating that the shared transmission is active by: de-asserting, at the output, the first signal for a period that ends after the receive datapath finishes sending delayed receive data.

14. The system of claim 8 , wherein the receive datapath comprises a delay circuit to store delayed received data.

15. The system of claim 14 , wherein the delay circuit comprises: a delay line to hold receive data for a period of time; and a delay logic to adjust the period of time that the delay line holds receive data.

16. The system of claim 15 , wherein the delay logic is to initiate the period of time that the delay line holds the receive data responsive to a collision signal.

17. The system of claim 8 , wherein the delaying some of the moving of the receive data until after the delay period comprises: delaying some of the moving of the receive data until after a uniform delay period.

18. The system of claim 8 , comprising a system-in-a-package (SiP), wherein the SiP comprises:

a physical layer side of the system;

a link layer side of the system; and

the interface,

wherein the interface operatively couples the physical layer side of the system and the link layer side of the system.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2019
From: IYER, VENKAT; CHEN, DIXON; ZANG, JOHN JUNLING; AKKIHAL, SHIVANAND I.
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 050732/0438 →
Cited By (1)
US 12,701,021