IP Library Granted Patent US 11,693,724
Granted Patent B2
US 11,693,724 · App. 16/654,739 · Granted Jul 4, 2023

Bit error rate estimation and error correction and related systems, methods, devices

Inventors: Dixon Chen (Guangdong, CN); Jiachi Yu (Guangdong, CN); Kevin Yang (Guangdong, CN)
Assignee: Microchip Technology Incorporated
G06F11/076G06F11/0793G06F11/1608G06F11/322H03M5/12H04L1/20H04L1/205H04L25/4904
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Quick Facts
Patent No.
US 11,693,724
App. No.
16/654,739
Granted
Jul 4, 2023
Kind
B2
Abstract

Physical layer devices and related methods for determining Bit Error Rates (BERs) and correcting errors in signals received through shared transmission media of wireless local area networks are disclosed. A physical layer device is configured to identify coding violations in received signal, determine a rate of the coding violations in the signal, and estimate a BER of the signal to be equal to the determined rate of the coding violations. A physical layer device is configured to invert a half symbol immediately preceding or immediately following a coding violation based, at least in part, on signal integrities of the half symbol immediately preceding and the half symbol immediately following the coding violation to correct a bit error.

Claims (40)

1. A physical layer device, comprising:

an input to receive a signal from a shared transmission medium of a wired local area network, the shared transmission medium of the wired local area network comprising a physical medium that is a communication path between nodes that are part of the wired local area network, the nodes including respective instances of physical layer devices; and

one or more processors to, at the physical layer device and in a physical layer of an Open Systems Interconnection (OSI) model:

identify coding violations in the signal received via the shared transmission medium of the wired local area network, the coding violations including two-level differential Manchester Encoding (DME) violations wherein signal transitions are not detected at respective clock transitions;

determine a rate of the coding violations in the signal; and

estimate a bit error rate of the signal to be the determined rate of the coding violations.

2. The physical layer device of claim 1 , the one or more processors to correct one or more half symbols adjacent to the identified coding violations in the signal.

3. The physical layer device of claim 2 , the one or more processors to correct the one or more half symbols based on signal integrities of a preceding symbol preceding the coding violation and a following symbol following the coding violation.

4. A physical layer device, comprising:

an input to receive a signal from a shared transmission medium of a wired local area network, the shared transmission medium of the wired local area network comprising a physical medium that is a communication path between nodes that are part of the wired local area network, the nodes including respective instances of physical layer devices; and

one or more processors to, in a physical layer of an Open Systems Interconnection (OSI) model:

identify a coding violation in the received signal, the coding violation including a two-level differential Manchester Encoding (DME) violation wherein a signal transition is not detected at a clock transition;

determine a preceding signal integrity of a preceding half symbol immediately preceding the coding violation;

determine a following signal integrity of a following half symbol immediately following the coding violation;

select one of the preceding half symbol or the following half symbol based, at least in part, on the preceding signal integrity and the following signal integrity; and

invert the selected one of the preceding half symbol or the following half symbol to correct the received signal.

5. The physical layer device of claim 4 , wherein the signal integrity is a signal amplitude of the preceding half symbol and the following half symbol.

6. The physical layer device of claim 5 , wherein the signal integrity is a difference between a measured amplitude and an expected amplitude.

7. The physical layer device of claim 4 , wherein the signal integrity is a signal waveform shape integrity of the preceding half symbol and the following half symbol.

8. The physical layer device of claim 7 , wherein the signal waveform shape integrity includes a difference between a determined signal waveform shape of the signal and an expected signal waveform shape.

9. A method of estimating a bit error rate (BER) of a signal, the method comprising, in a physical layer of an Open Systems Interconnection (OSI) model:

identifying coding violations in a signal received via a shared transmission medium of a wired local area network, the shared transmission medium of the wired local area network comprising a physical medium that is a communication path between nodes that are part of the wired local area network, the nodes including respective instances of physical layer devices, the coding violations including two-level differential Manchester Encoding (DME) violations wherein signal transitions are not detected at respective clock transitions;

determining a rate of the coding violations in the signal; and

estimating a BER of the signal to be the determined rate of the coding violations in the signal.

10. The method of claim 9 , comprising identifying signal integrities of a half symbol before and of a half symbol after a coding violation.

11. The method of claim 10 , wherein identifying signal integrities of a half symbol before and of a half symbol after a coding violation includes identifying signal amplitude integrities of the half symbol before and of the half symbol after the coding violation.

12. The method of claim 10 , wherein identifying signal integrities of a half symbol before and of a half symbol after a coding violation includes identifying signal waveform shape integrities of the half symbol before and of the half symbol after the coding violation.

13. The method of claim 10 , comprising:

determining that one of the half symbol before or the half symbol after the coding violation has a signal integrity that differs from an expected signal integrity more than the other of the half symbol before or the half symbol after; and

correcting the one of the half symbol before or the half symbol after that has the signal integrity that differs more than the other.

14. The method of claim 13 , wherein correcting the one of the half symbol before or the half symbol after comprises inverting the one of the half symbol before or the half symbol after.

15. A method of performing error correction on a received signal, the method comprising, in a physical layer of an Open Systems Interconnection (OSI) model:

identifying a coding violation in a received signal, the received signal received through a shared transmission medium of a wired local area network, the shared transmission medium of the wired local area network comprising a physical medium that is a communication path between nodes that are part of the wired local area network, the nodes including respective instances of physical layer devices, the coding violation including a two-level differential Manchester Encoding (DME) violation wherein a signal transition is not detected at a clock transition;

determining a preceding signal integrity of a preceding symbol immediately preceding the coding violation;

determining a following signal integrity of a following symbol immediately following the coding violation;

selecting one of the preceding symbol or the following symbol based, at least in part, on the preceding signal integrity and the following signal integrity; and

inverting the selected one of the preceding symbol or the following symbol to correct the received signal.

16. The method of claim 15 , wherein determining the preceding signal integrity and determining the following signal integrity comprises determining signal amplitude integrities of the preceding symbol and the following symbol.

17. The method of claim 15 , wherein selecting one of the preceding symbol or the following symbol based, at least in part, on the preceding signal integrity and the following signal integrity comprises selecting the one of the preceding symbol or the following symbol that has an amplitude that is furthest from an expected amplitude.

18. The method of claim 15 , wherein determining the preceding signal integrity and determining the following signal integrity comprises determining signal waveform shape integrities of the preceding symbol and the following symbol.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2019
From: CHEN, DIXON; YU, JIACHI; YANG, KEVIN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 050737/0087 →