Wiring substrate, semiconductor package having the wiring substrate, and manufacturing method thereof
Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.
1. A semiconductor package comprising:
a first wiring;
a semiconductor device comprising a device top side, a device bottom side opposite to the device top side, a first terminal adjacent to the device bottom side and coupled to the first wiring, a second terminal adjacent to the device top side, and a third terminal adjacent to the device top side laterally separated from the second terminal;
an insulating film over the second terminal and the third terminal;
a first layer over the insulating film and over the second terminal but not over the third terminal;
an opening in the first layer over the second terminal;
a first via that extends through the insulating film to expose at least a portion of the third terminal;
a second via that extends from the opening through the insulating film to expose at least a portion of the second terminal; and
a second layer having a first portion within the first via and having a second portion over the first layer and within the opening and the second via, wherein:
the first portion of the second layer comprises a first wiring route;
the second portion of the second layer and the first layer comprises a second wiring route; and
the first wiring route is devoid of the first layer.
2. The semiconductor package according to claim 1 , wherein:
the second portion of the second layer overlaps an upper surface of the first layer;
the second portion of the second layer has a first thickness overlapping the upper surface of the first layer and a second thickness in the second via; and
the first thickness is less than the second thickness.
3. The semiconductor package wiring substrate according to claim 2 , wherein
the first layer has a third thickness; and
the first thickness is less than the third thickness.
4. The semiconductor package according to claim 1 , wherein:
the first layer comprises a patterned metal plate.
5. The semiconductor package according to claim 1 , wherein:
a top surface of the insulating film has a depressed portion between the second via and the first layer.
6. The semiconductor package according to claim 1 , wherein:
the opening has a first width; and
the second via has a second width different than the first width.
7. The semiconductor package according to claim 1 , wherein:
the first layer has a side surface defining the opening;
the side surface has a first portion having a first slope;
the side surface has a second portion coupled to the first portion having a second slope; and
the second sloped is different from the first slope.
8. A semiconductor package comprising:
a semiconductor device comprising a device top side, a device bottom side opposite to the device top side, a first terminal over the device bottom side, a second terminal over the device top side, and a third terminal over the device top side spaced apart from the second terminal;
an insulating film located over the second terminal and the third terminal;
a first layer over the insulating film and over the second terminal but not over the third terminal, wherein the first layer comprises openings extending through the first layer above the second terminal;
a first via that extends through the insulating film to expose the third terminal;
second vias that extend from the openings through the insulating film to expose the second terminal; and
a second layer having a first portion within the first via and having a second portion over the first layer and within the openings and the second vias, wherein:
the first portion of the second layer comprises a lower current wiring route for the semiconductor device; and
the second portion of the second layer and the first layer comprise a higher current route for the semiconductor device.
9. The semiconductor package according to claim 8 , wherein:
the second portion of the second layer overlaps an upper surface of the first layer;
the second portion of the second layer has a first thickness overlapping the upper surface of the first layer and a second thickness within the second vias; and
the first thickness is less than the second thickness.
10. The semiconductor package according to claim 8 , wherein:
the first via is laterally spaced apart from a proximate edge of the first layer.
11. The semiconductor package according to claim 8 , wherein:
the first layer comprises a metal plate attached to the insulating layer.
12. The semiconductor package according to claim 8 , wherein:
a top surface of the insulating film has a depressed portion between each of the second vias and the respective openings.
13. The semiconductor package according to claim 8 , wherein:
the openings each have a first width; and
the second vias each have a second width less than the first width.
14. The semiconductor package according to claim 8 , wherein:
the second portion of second layer overlaps side surfaces of the first layer in the openings.
15. A semiconductor package, comprising:
a first semiconductor device comprising a first terminal over a bottom side of the first semiconductor device, a second terminal over a top side of the first semiconductor device, and a third terminal over the top side of the first semiconductor device spaced apart from the second terminal;
a first insulating film over the third terminal;
a first layer over the second terminal but not over the third terminal;
a first via that extends through the first insulating film to expose at least a portion of the third terminal;
a second via that extends through the first layer to expose at least a portion of the second terminal;
a second layer having a first portion within the first via and having a second portion over the first layer and within the second via, wherein:
the first portion of the second layer comprises a first wiring route; and
the second portion of the second layer and the first layer comprises a second wiring route;
a second semiconductor device having a fourth terminal electrically connected to the third terminal of the first semiconductor device through the first wiring route; and
a second insulating film embedding the first semiconductor device and the second semiconductor device, wherein:
the first semiconductor device comprises a power device; and
the second semiconductor device comprises a control device.
16. The semiconductor package according claim 15 , wherein:
the second insulating film is interposed between first layer and the second terminal and between the first insulating film and third terminal; and
the first wiring route is devoid of the first layer.
17. The semiconductor package according to claim 15 , wherein:
the second portion of the second layer overlaps an upper surface of the first layer;
the second portion of the second layer has a first thickness overlapping the upper surface of the first layer and a second thickness in the second via; and
the first thickness is less than the second thickness.
18. The semiconductor package according to claim 17 , wherein
the first layer has a third thickness; and
the first thickness is less than the third thickness.
19. The semiconductor package according to claim 15 , wherein:
the first layer comprises a patterned metal plate.
20. The semiconductor package according to claim 15 , wherein: the first layer and the second layer are different in conductivity from each other.