Media access for time-sensitive and best efforts data packets, and related systems, methods and devices
Disclosed embodiments relate, generally, to traffic shaping at a network segment having a shared bus. Some embodiments relate to performing aspects of the traffic shaping at a physical layer device. In some cases, transmit timeslot signaling may be tuned at a physical layer device to create transmit timeslots that are aligned with the traffic shaping profile.
1. A method of performing traffic shaping for an Ethernet network segment, the method comprising:
performing transmit timeslot signaling from a physical layer to a media access control unit of a link layer of a network segment;
adjusting the transmit timeslot signaling responsive to detecting a scheduled timeslot of a bus cycle of the network segment;
performing a data transmission to a shared bus of the network segment during the scheduled timeslot;
after performing the data transmission, starting a yielding of shared timeslots for a number of bus cycles; and
detecting that a yielded timeslot was not used.
2. The method of claim 1 , wherein the performing the transmit timeslot signaling comprises: tuning carrier sense signaling between the physical layer and the link layer of the network segment.
3. The method of claim 2 , wherein the tuning the carrier sense signaling comprises:
asserting and/or de-asserting an emulated carrier sense signaling.
4. The method of claim 1 , further comprising:
receiving an event associated with the scheduled timeslot; and
detecting the scheduled timeslot responsive to the event.
5. The method of claim 1 , wherein the performing the data transmission to the shared bus of the network segment during the scheduled timeslot comprises:
receiving transmit data from the link layer of the network segment; and
providing the transmit data to the shared bus during the scheduled timeslot.
6. The method of claim 1 , further comprising:
receiving an event associated with a shared timeslot; and
determining that the shared timeslot should be claimed.
7. A method of performing traffic shaping for an Ethernet network segment, the method comprising:
performing transmit timeslot signaling from a physical layer to a media access control unit of a link layer of a network segment;
adjusting the transmit timeslot signaling responsive to detecting a scheduled timeslot of a bus cycle of the network segment;
performing a data transmission to a shared bus of the network segment during the scheduled timeslot;
receiving an event associated with a shared timeslot; and
determining that the shared timeslot should be claimed, wherein the determining the scheduled timeslot should be claimed comprises:
counting a number of bus cycles since last claiming a timeslot; and
determining that the counted number of bus cycles meets a threshold.
8. The method of claim 1 , comprising:
ending the yielding of the shared timeslots prior to the number of bus cycles.
9. The method of claim 8 , wherein the ending the yielding of the shared timeslots prior to the number of bus cycles comprises resetting a yield count according to a pre-specified priority.
10. The method of claim 1 , wherein the detecting that a yielded timeslot was not used comprises:
observing no carrier activity at the shared bus during the yielded timeslot.
11. The method of claim 1 , further comprising:
synchronizing a local clock to a master clock using a precision time protocol; and
using a synchronized local clock to generate events associated with a schedule of timeslots.
12. A device, comprising:
a timeslot signaling circuitry, the timeslot signaling circuitry to perform transmit timeslot signaling from a physical layer device to a media access control unit of a link layer responsive to scheduled timeslots of a bus cycle, wherein the timeslot signaling circuitry comprises a priority logic to:
start a yielding of shared timeslots for a number of bus cycles; and
detect that a yielded timeslot of the shared timeslots was not used; and
a transmission circuitry, the transmission circuitry to:
receive transmit data from the link layer; and
move the transmit data toward a shared bus according to a timeslot of the scheduled timeslots.
13. The device of claim 12 ,
the priority logic to determine that the timeslot of the scheduled timeslots should be claimed, wherein the timeslot signaling circuitry comprises a tuning circuitry, the tuning circuitry to assert and de-assert emulated carrier sense signaling responsive to the determination by the priority logic.
14. The device of claim 13 , the priority logic to determine that the timeslot should be claimed responsive to an event associated with the timeslot.
15. A device, comprising:
a timeslot signaling circuitry, the timeslot signaling circuitry to perform transmit timeslot signaling from a physical layer device to a media access control unit of a link layer responsive to scheduled timeslots of a bus cycle; and
a transmission circuitry, the transmission circuitry to:
receive transmit data from the link layer; and
move the transmit data toward a shared bus according to a timeslot of the scheduled timeslots,
wherein the timeslot signaling circuitry comprises:
priority logic to determine that a timeslot of the scheduled timeslots should be claimed; and
tuning circuitry to assert and de-assert emulated carrier sense signaling responsive to the determination by the priority logic, the priority logic to determine that the timeslot should be claimed by:
counting a number of bus cycles since last claiming the timeslot; and
determine that the counted number of bus cycles meets a threshold.
16. The device of claim 12 , the priority logic to:
end the yielding of the shared timeslots prior to the number of bus cycles.
17. The device of claim 12 , wherein the priority logic is to reset a yield count according to a pre-specified priority to end the yielding of the shared timeslots prior to the number of bus cycles.
18. The device of claim 12 , the timeslot signaling circuitry to de-assert the transmit timeslot signaling during the timeslot of the scheduled timeslots for a number of bus cycles after the transmission circuitry accesses the shared bus.
19. The device of claim 12 , further comprising sensing circuitry to provide carrier activity signaling indicative of carrier activity at the shared bus.
20. The device of claim 19 , the timeslot signaling circuitry to suppress signaling a timeslot responsive to the carrier activity signaling being indicative of carrier activity at the shared bus during the yielded timeslot of the shared timeslots.
21. The device of claim 19 , wherein the timeslot signaling circuitry is to detect that the yielded timeslot of the shared timeslots was not used responsive to the carrier activity signaling being indicative of no carrier activity at the shared bus during the yielded timeslot.
22. The device of claim 12 , further comprising:
a reception circuitry, the reception circuitry to move receive data from the shared bus toward the link layer, and
the timeslot signaling circuitry to suppress signaling another timeslot responsive to detecting that receive data is being moved by the reception circuitry during the another timeslot.
23. A system for performing traffic shaping at a network segment, the system comprising:
a scheduler provided at a link layer side of the system, the scheduler to generate events to indicate scheduled timeslots responsive to a synchronized local clock;
a media access control unit provided at the link layer side of the system, the media access control unit to provide transmit data; and
a timeslot signaling circuitry provided at a physical layer side of the system, the timeslot signaling circuitry to create transmit timeslots for the media access control unit by asserting and de-asserting emulated carrier sense signaling responsive to the generated events, wherein the timeslot signaling circuitry comprises a priority logic to:
start a yielding of shared timeslots for a number of bus cycles; and
detect that a yielded timeslot of the shared timeslots was not used.
24. The system of claim 23 , further comprising an interface arranged between the link layer side of the system and the physical layer side of the system.
25. The system of claim 23 , wherein an event path operatively coupling the timeslot signaling circuitry to the scheduler includes an interface between the link layer side and the physical layer side of the system.
26. The system of claim 23 , wherein an event path operatively coupling the timeslot signaling circuitry to the scheduler does not include an interface between the link layer side and the physical layer side of the system.
27. The system of claim 23 , the priority logic to end the yielding of the shared timeslots prior to the number of bus cycles.