Integrated circuit with doped low-k sidewall spacers for gate stacks
Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.
1. A device comprising:
a gate stack disposed on a substrate;
a first sidewall spacer formed of a low-k dielectric material and disposed on the gate stack, wherein the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a porous low-k dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant; and
a second sidewall spacer disposed on the gate stack and extending under the first sidewall spacer such that the first sidewall spacer is prevented from physically contacting the substrate by the second sidewall spacer.
2. The device of claim 1 , wherein the dopant is the p-type dopant, the p-type dopant selected from the group consisting of B and BF 2 .
3. The device of claim 1 , wherein the dopant is the n-type dopant, the n-type dopant selected from the group consisting of P and As.
4. The device of claim 1 , wherein the second sidewall spacer is disposed directly on the sidewall of the gate stack such that the second sidewall spacer is closer to the gate stack than the first sidewall spacer.
5. The device of claim 1 , further comprising a contact etch stop layer disposed directly on a sidewall of the first sidewall spacer, the contact etch stop layer having a top surface facing away from the substrate and the first sidewall spacer having a top surface facing away from the substrate, wherein the top surface of the contact etch stop layer and the top surface of the first sidewall surface are planarized.
6. The device of claim 1 , wherein the gate stack includes:
a gate dielectric layer;
a capping layer disposed on the gate dielectric layer;
a barrier layer disposed on the capping layer;
a work function metal layer disposed on the barrier layer; and
a metal fill layer disposed on the work function metal layer.
7. A device comprising:
a first gate stack disposed on a substrate;
a first sidewall spacer disposed along an edge of the first gate stack, the first sidewall spacer having an L-shaped profile that defines a recess; and
a second sidewall spacer formed of a low-k dielectric material and disposed on the first sidewall spacer within the recess defined by the L-shaped profile of the first sidewall spacer, wherein the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a dielectric material and a dopant selected from the group consisting of an n-type dopant and a p-type dopant,
wherein the low-k dielectric material has at least one void therein.
8. The device of claim 7 , wherein the dielectric material includes a material selected from the group consisting of a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and a semiconductor oxycarbonitride.
9. The device of claim 7 , further comprising a contact etch stop layer disposed along a physically contacting a sidewall of the first sidewall spacer and a sidewall of the second sidewall spacer.
10. The device of claim 9 , wherein the second sidewall spacer has a first sidewall and opposing second sidewall, wherein a bottom surface of the second sidewall spacer extends from the first sidewall to the second sidewall of the second sidewall spacer, and
wherein the first sidewall spacer physically contacts the entire first sidewall and bottom surface of the second sidewall spacer, and
wherein the contact etch stop layer physically contacts the entire second of the second sidewall spacer.
11. The device of claim 9 , wherein the first sidewall spacer has a bottom surface physically contacting the substrate and an opposing top surface such that a length of the first sidewall spacer is measured from the bottom surface of the first sidewall spacer to the top surface of the first sidewall spacer, and
wherein the contact etch stop layer has a bottom surface physically contacting the substrate and an opposing top surface such that a length of the contact etch stop layer is measured from the bottom surface of the contact etch stop layer to the top surface of the contact etch stop layer, wherein the first sidewall spacer and the contact etch stop layer have the same lengths.
12. The device of claim 11 , further comprising:
a second gate stack disposed on the substrate;
a third sidewall spacer formed of the low-k dielectric material and disposed on the second gate stack;
an interlayer dielectric layer disposed over the first gate stack and the second gate stack;
a source/drain feature disposed in the substrate; and
a contact extending through the interlayer dielectric layer to the source/drain feature, wherein the contact etch stop layer has a sidewall extending the entire length of the contact etch from the bottom surface of the contact etch stop layer to the top surface of the contact etch stop layer, the contact physically contacting the entire sidewall of the contact etch stop layer.
13. A device comprising:
a substrate;
a gate stack disposed on the substrate;
a first sidewall spacer disposed on a side surface of the gate stack, wherein the first sidewall spacer includes a low-k dielectric material, wherein the low-k dielectric material includes a void therein and a dopant;
a second sidewall spacer disposed between the first sidewall spacer and the substrate such that the second sidewall spacer prevents the low-k dielectric material from interface with the substrate; and
a source/drain contact disposed such that the sidewall spacer is disposed between the source/drain contact and the gate stack.
14. The device of claim 13 , wherein the dopant is selected from the group consisting of B, BF 2 , P and As.
15. The device of claim 13 , further comprising a contact etch stop layer disposed between the source/drain contact and the spacer layer.
16. The device of claim 15 , further comprising a source/drain region disposed on the substrate to which the source/drain contact is coupled, and
wherein the contact etch stop layer interfaces with the source/drain region.
17. The device of claim 13 , wherein the low-k dielectric material is a material having a dielectric constant of 1 to less than 3.9, wherein the low-k dielectric material includes a dielectric material selected from the group consisting of a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, and a semiconductor oxycarbonitride.
18. The device of claim 13 , wherein the second sidewall interfaces with the side surface of the gate stack,
wherein the second sidewall spacer has an L-shaped profile that defines a recess, and
wherein the low-k dielectric material is disposed on the second sidewall spacer within the recess defined by the L-shaped profile of the second sidewall spacer, wherein the dopant is selected from the group consisting of an n-type dopant and a p-type dopant.