IP Library › Granted Patent US 10,804,309
Granted Patent B2
US 10,804,309 · App. 16/694,195 · Granted Oct 13, 2020

Photodetector

Inventors: Yusuke Otake (Kanagawa, JP); Akira Matsumoto (Kanagawa, JP); Junpei Yamamoto (Kanagawa, JP); Ryusei Naito (Nagasaki, JP); Masahiko Nakamizo (Kanagawa, JP); Toshifumi Wakano (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/1463H01L27/1461H01L27/1464H01L27/14607H01L27/14609H01L27/14623H01L27/14634H01L27/14636H01L31/02162H01L31/02327H01L31/107H01L27/14612H01L27/14627
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,804,309
App. No.
16/694,195
Granted
Oct 13, 2020
Kind
B2
Abstract

A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.

Claims (88)

1. A sensor, comprising:

a first substrate including:

a first semiconductor layer including:

a first avalanche photodiode including a first cathode region and a first anode region; and

a first isolation region,

a first wiring layer including:

a first wiring;

a first via, wherein the first cathode region is electrically connected to the first wiring through the first via;

a second wiring; and

a second via, wherein the first anode region is electrically connected to the second wiring through the second via; and

a second substrate stacked on the first substrate, the second substrate including:

a second wiring layer including:

a third wiring directly bonded to the first wiring; and

a fourth wiring directly bonded to the second wiring; and

a second semiconductor layer, wherein the first anode region is disposed between the first cathode region and the first isolation region.

2. The sensor according to claim 1 , wherein the first and third wirings overlap the first avalanche photodiode.

3. The sensor according to claim 2 , wherein the second and fourth wirings at least partially overlap the first avalanche photodiode.

4. The sensor according to claim 1 , wherein the first isolation region includes a first metal film.

5. The sensor according to claim 4 , wherein the first isolation region includes a void region at least partially surrounded by the first metal film.

6. The sensor according to claim 1 , further comprising an on-chip lens disposed on the first semiconductor layer.

7. The sensor according to claim 6 , wherein the on-chip lens is disposed on a light incident surface of the first semiconductor layer.

8. The sensor according to claim 6 , wherein the on-chip lens is disposed on a first film attached to the first isolation region.

9. The sensor according to claim 4 , wherein the first isolation region includes a second film attached to the first metal film.

10. The sensor according to claim 9 , wherein the first film is attached to the second film.

11. The sensor according to claim 7 , wherein the first isolation region penetrates the light incident surface of the first semiconductor layer.

12. A sensor, comprising:

a first substrate including:

a first semiconductor layer including:

a first avalanche photodiode including a first contact region and a second contact region; and

a first isolation region;

a first wiring layer including:

a first wiring;

a first via, wherein the first contact region is electrically connected to the first wiring through the first via;

a second wiring; and

a second via, wherein the second contact region is electrically connected to the second wiring through the second via; and

a second substrate stacked on the first substrate, the second substrate including:

a second wiring layer including:

a third wiring directly bonded to the first wiring; and

a fourth wiring directly bonded to the second wiring; and

a second semiconductor layer, wherein the first contact region is disposed between the second contact region and the first isolation region.

13. The sensor according to claim 12 , wherein the first and third wirings overlap the first avalanche photodiode.

14. The sensor according to claim 13 , wherein the second and fourth wirings at least partially overlap the first avalanche photodiode.

15. The sensor according to claim 12 , wherein the first isolation region includes a first metal film.

16. The sensor according to claim 15 , wherein the first isolation region includes a void region at least partially surrounded by the first metal film.

17. The sensor according to claim 12 , further comprising an on-chip lens disposed on the first semiconductor layer.

18. The sensor according to claim 17 , wherein the on-chip lens is disposed on a light incident surface of the first semiconductor layer.

19. The sensor according to claim 17 , wherein the on-chip lens is disposed on a first film attached to the first isolation region.

20. A sensor, comprising:

an on-chip lens;

a first substrate including:

a first semiconductor layer including:

a first avalanche photodiode including a first contact region and a second contact region; and

a first wiring layer including:

a first wiring;

a first via, wherein the first contact region is electrically connected to the first wiring through the first via;

a second wiring; and

a second via; wherein the second contact region is electrically connected to the second wiring through the second via; and

a second substrate stacked on the first substrate, the second substrate including:

a second wiring layer including:

a third wiring directly bonded to the first wiring; and

a fourth wiring directly bonded to the second wiring; and

a second semiconductor layer, wherein the first contact region is disposed between the second contact region and the first isolation region, and wherein the on-chip lens is disposed on the first substrate.

21. The sensor according to claim 20 , wherein the first and third wirings overlap the first avalanche photodiode.

22. The sensor according to claim 21 , wherein the second and fourth wirings at least partially overlap the first avalanche photodiode.

23. The sensor according to claim 20 , wherein the first isolation region includes a first metal film.

24. The sensor according to claim 23 , wherein the first isolation region includes a void region at least partially surrounded by the first metal film.

25. The sensor according to claim 20 , wherein the on-chip lens is disposed on the first semiconductor layer.

26. The sensor according to claim 25 , wherein the on-chip lens is disposed on a light incident surface of the semiconductor layer.

27. The sensor according to claim 25 , wherein the on-chip lens is disposed on a first film attached to the first isolation region.

28. A time of flight system comprising:

a light source configured to emit light to an object;

a sensor, comprising:

a first substrate including:

a first semiconductor layer including:

a first avalanche photodiode including a first cathode region and a first anode region; and

a first isolation region;

a first wiring layer including:

a first wiring;

a first via, wherein the first cathode region is electrically connected to the first wiring through the first via;

a second wiring; and

a second via, wherein the first anode region is electrically connected to the second wiring through the second via, and

a second substrate stacked on the first substrate, the second substrate including:

a second wiring layer comprising:

a third wiring directly bonded to the first wiring; and

a fourth wiring directly bonded to the second wiring; and

a second semiconductor layer, wherein the first anode region is disposed between the first cathode region and the first isolation region.

29. The time of flight system according to claim 28 , wherein the first and third wirings overlap the first avalanche photodiode.

30. The time of flight system according to claim 29 , wherein the second and fourth wirings at least partially overlap the first avalanche photodiode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2020
From: OTAKE, YUSUKE; MATSUMOTO, AKIRA; YAMAMOTO, JUNPEI; NAITO, RYUSEI; NAKAMIZO, MASAHIKO; WAKANO, TOSHIFUMI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 052499/0237 →
Priority Claims (4)
JP 2016-204475 · Oct 18, 2016 · national
JP 2017-039336 · Mar 2, 2017 · national
JP 2017-114380 · Jun 9, 2017 · national
JP 2017-152060 · Aug 4, 2017 · national
Continuity (3)
Continuation 16409494 · May 10, 2019
Continuation 16060509
Related Publication 20200091208A1 · Mar 19, 2020
Cited By (3)
US 12,419,126 US 12,581,761 US 12,607,723