Sparse matrix optimization mechanism
An apparatus to facilitate matrix processing is disclosed. The apparatus comprises a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, examine a first block of the sub-blocks to determine whether the first block comprises sparse data, select a first tile size upon a determination that the first block comprises sparse data and generate output matrix data based on the first tile size.
1. An apparatus to facilitate matrix processing, comprising:
a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, retrieve bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks, examine sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed, select a first tile size for processing of the sub-blocks upon a determination that the sub-block bits indicate that each sub-block in the first block comprises sparse data and process the sub-blocks to generate output matrix data.
2. The apparatus of claim 1 , wherein the first tile size comprises a size of the first block.
3. The apparatus of claim 2 , wherein the second tile size comprises a size of a sub-block.
4. The apparatus of claim 1 , wherein the matrix accelerator selects the second tile size upon a determination that at least one sub-block in the first block does not comprise sparse data.
5. The graphics processor of claim 1 , wherein the first tile size comprises a size of the first block.
6. The graphics processor of claim 5 , wherein the second tile size comprises a size of a sub-block.
7. A method to facilitate matrix processing, comprising:
receiving input matrix data;
transforming the input matrix data into a plurality of sub-blocks;
retrieving bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks;
examining sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed block comprises sparse data;
selecting a first tile size for processing of the sub-blocks upon a determination that the sub-block bits indicate that each sub-block in the first block comprises sparse data; and
processing the sub-blocks to generate output matrix data.
8. The method of claim 7 , wherein the first tile size comprises a size of the first block.
9. The method of claim 8 , wherein the second tile size comprises a size of a sub-block.
10. The method of claim 7 , further comprising:
selecting the second tile size upon a determination that at least one sub-block in the first block does not comprise sparse data.
11. A graphics processor comprising:
a matrix accelerator to receive input matrix data, transform the input matrix data into a plurality of sub-blocks, retrieve bitmap data having a plurality sub-block bits, each associated with one of the plurality of sub-blocks, examine sub-block bits associated with adjacent sub-blocks in a first block to determine a tile size that is to be processed, select a first tile size for processing of the sub-blocks upon a determination that the sub-block bits indicate that each sub-block in the first block comprises sparse data and process the sub-blocks to generate output matrix data; and
a systolic pipeline to generate output matrix data based on the first tile size.
12. The graphics processor of claim 11 , wherein the matrix accelerator selects the second tile size upon a determination that at least one sub-block in the first block does not comprise sparse data.