Surface-mount integrated circuit package with coated surfaces for improved solder connection
Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
1. A method for forming an integrated circuit (IC) package, the method comprising:
forming an IC package structure including a conductive terminal structure partially encapsulated by a mold compound such that a first side of the conductive terminal structure is covered by the mold compound and a second side of the conductive terminal structure opposite the first side of the conductive terminal structure has an exposed terminal structure surface;
forming a first coating of a first coating material on the exposed terminal structure surface;
performing a first cutting process to cut a channel extending through a full thickness of the conductive terminal structure and defining an opposing pair of terminal structure sidewall surfaces on opposite sides of the channel, each of the opposing pair of terminal structure sidewall surfaces having a full height defined by the full thickness of the conductive terminal structure;
forming a second coating of a second coating material covering the full height of each of the opposing pair of terminal structure sidewall surfaces to define an opposing pair of coated terminal structure sidewall surfaces;
wherein the first coating material and the second coating material comprise solder-enhancing materials; and
performing a second cutting process through the channel to divide the IC package structure, wherein a second cut width of the second cutting process is smaller than a width of an opening between the opposing pair of coated terminal structure sidewall surfaces so that the second cutting process does not cut through the second coating material on the opposing pair of coated terminal structure sidewall surfaces.
2. The method of claim 1 , wherein the first cutting process has a first cutting width, and the second cut width is smaller than the first cutting width.
3. The method of claim 1 , further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 80% of the full height of the respective coated terminal structure sidewall surface.
4. The method of claim 1 , further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 90% of the full height of the respective coated terminal structure sidewall surface.
5. The method of claim 1 , further comprising, after the second cutting process to divide the IC package structure, performing a soldering process on a respective one of the coated terminal structure sidewall surfaces to form a solder having a solder connection area covering at least 100% of the full height of the respective coated terminal structure sidewall surface.
6. The method of claim 1 , wherein the first coating material and the second coating material comprise the same material.
7. The method of claim 6 , wherein the first coating material and the second coating material comprise tin.
8. The method of claim 1 , wherein the first coating material and the second coating material comprise different materials.
9. The method of claim 1 , wherein forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises immersing the full height of each exposed terminal structure sidewall surface in the second coating material.
10. The method of claim 1 , wherein forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises performing a tin immersion process to coat the full height of each exposed terminal structure sidewall surface with tin.
11. The method of claim 1 , wherein:
forming the first coating of the first coating material on the exposed terminal structure surface comprises performing a tin electroplating process; and
forming the second coating of the second coating material over the full height of each exposed terminal structure sidewall surface comprises performing a tin immersion process.
12. The method of claim 1 , wherein each exposed terminal structure sidewall surface lies in a respective single plane.
13. The method of claim 1 , wherein the IC package structure comprises a flat no-leads structure.
14. The method of claim 1 , wherein the IC package structure comprises a dual flat no-leads (DFN) structure.
15. The method of claim 1 , wherein the IC package structure comprises a quad flat no-leads (QFN) structure.
16. The method of claim 1 , wherein the second coating of the second coating material covers the first coating material on the exposed terminal structure surface, to form a combined coating including the first coating material and the second coating material over the exposed terminal structure surface.