Apparatus with an internal-operation management mechanism
Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.
1. An apparatus, comprising:
a detection circuit configured to detect a condition associated with two or more accesses to a memory address or a memory region within a predetermined duration; and
a scheduling circuit coupled to the detection circuit, the scheduling circuit configured to:
generate a scheduling output based on the detected condition, wherein the scheduling output is communicated to a host coupled to the apparatus for securing a scheduled duration of inactivity for the apparatus, and
trigger execution of one or more memory-internal operations during the scheduled duration.
2. The apparatus of claim 1 , wherein the one or more memory-internal operations include one or more row hammer refresh operations.
3. The apparatus of claim 1 , wherein the scheduling output represents a command address parity error, wherein the scheduling output is independent of an actual command address parity.
4. The apparatus of claim 1 , wherein the scheduling output represents a cyclic redundancy check (CRC) error, wherein the scheduling output is independent of an actual CRC data.
5. The apparatus of claim 1 , wherein the scheduling output is a predetermined state or value for an alert signal that reports an error condition in response to the detected condition, wherein the scheduling output is independent of the condition.
6. The apparatus of claim 5 , wherein the scheduling output corresponds to an ALERT #signal according to a Double Data Rate (DDR) protocol.
7. The apparatus of claim 1 , wherein the scheduling output includes one or more flipped data (DQ) bits.
8. The apparatus of claim 7 , wherein the scheduling output is for triggering an error correction process at the host.
9. The apparatus of claim 1 , wherein the scheduling output is configured to report a temperature level higher than an actual temperature reading for the apparatus.
10. The apparatus of claim 1 , further comprising a register device.
11. The apparatus of claim 10 , wherein the apparatus comprises a register clock driver.
12. The apparatus of claim 1 , wherein the apparatus further comprises a memory array having a plurality of memory cells.
13. The apparatus of claim 1 , wherein the apparatus comprises a dynamic random-access memory (DRAM).
14. The apparatus of claim 1 , wherein the scheduling circuit includes a transistor connected to a corresponding connection port and the scheduling output, wherein the transistor is configured to force an output level at the connection port to a predetermined level when the scheduling output represents the detected condition.
15. A method of operating an apparatus, the method comprising:
receiving a command for an operation from a host coupled to the apparatus;
detecting a condition based on the command, wherein the condition is associated with two or more accesses to a memory address or a memory region within a predetermined duration;
generating a scheduling output based on the detected condition, wherein the scheduling output is communicated to the host for securing a scheduled duration of inactivity for the apparatus; and
initiating one or more internal operations during the scheduled duration.
16. The method of claim 15 , further comprising executing the one or more internal operations during the scheduled duration, wherein the one or more internal operations include one or more row hammer refresh operations.
17. The method of claim 15 , wherein generating the scheduling output includes communicating to the host a signal representative of an error condition in response to the detected condition, wherein the scheduling output is independent of the error condition.
18. The method of claim 15 , wherein generating the scheduling output includes flipping one or more data (DQ) bits communicated with the host.
19. The method of claim 15 , wherein generating the scheduling output includes reporting a temperature level higher than an actual temperature reading for the apparatus.
20. A system, comprising:
a host configured to command a memory operation; and
a memory device coupled to the host, the memory device configured to:
detect a condition based on the memory operation, wherein the condition is associated with two or more accesses to a memory address or a memory region within a predetermined duration;
generate a scheduling output based on the detected condition, wherein the scheduling output is communicated to the host for securing a scheduled duration of inactivity for the memory device; and
initiate one or more memory-internal operations during the scheduled duration;
wherein:
the host is configured to pause scheduled operations for the scheduled duration including and/or subsequent to the memory operation.
21. The system of claim 20 , wherein:
the scheduling output represents an error condition;
the memory device is configured to:
generate the scheduling output based on the detected condition and independent of the error condition, and
execute the one or more memory-internal operations during the scheduled duration; and
the host is configured to implement an error recovery process during the scheduled duration based on the scheduling output from the memory device.