Precise programming method and apparatus for analog neural memory in an artificial neural network
Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
1. A method comprising:
performing a first programming process comprising multiple program-verify cycles, wherein a programming voltage of increasing magnitude is applied to a terminal of a selected non-volatile memory cell in program-verify cycles after the first program-verify cycle, wherein each program-verify cycle comprises:
applying a first voltage to one of an erase gate terminal and a control gate terminal of the selected non-volatile memory cell;
measuring a first current that results through the selected non-volatile memory cell;
applying a second voltage to the one of the erase gate terminal and the control gate terminal of the selected non-volatile memory cell;
measuring a second current that results through the selected non-volatile memory cell;
determining a slope value based on the first voltage, the second voltage, the first current, and the second current; and
determining a next programming voltage of the programming voltages of increasing magnitude for the next program-verify cycle based on the determined slope value.
2. The method of claim 1 , further comprising:
programming the selected non-volatile memory cell using the next programming voltage.
3. The method of claim 2 , further comprising:
repeating the steps of determining a next programming voltage and programming the non-volatile memory cell using the next programming voltage until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.
4. A method comprising:
performing a first programming process comprising multiple program-verify cycles, wherein a programming voltage of increasing magnitude is applied to a terminal of a selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle,
wherein the step of performing a first programming process further comprises: when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.
5. The method of claim 4 , further comprising:
performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.
6. The method of claim 4 , wherein the selected non-volatile memory cell is a split-gate flash memory cell.
7. The method of claim 4 , wherein the selected non-volatile memory cell is in a vector-by-matrix multiplication array in an analog neural network.
8. A method comprising:
performing a first programming process comprising multiple program-verify cycles, wherein a programming voltage of increasing magnitude is applied to a terminal of a selected non-volatile memory cell in each program-verify cycle after the first program-verify cycle and wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value;
wherein when the current through the selected non-volatile memory cell during the read or verify operation is less than or equal to the first threshold current value, performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value, wherein the second programming process comprises applying voltage pulses of increasing magnitude to a control gate of the selected non-volatile memory cell, wherein the second programming process further comprises applying voltage pulses of decreasing magnitude to an erase gate of the selected non-volatile memory cell.
9. A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, the selected non-volatile memory cell comprising a floating gate, a control gate terminal, an erase gate terminal, and a source line terminal, the method comprising:
performing a first programming process comprising multiple program-verify cycles, wherein a first programming voltage of increasing magnitude is applied to the control gate of the selected non-volatile memory cell and a second programming voltage of decreasing magnitude is applied to the erase gate of the selected non-volatile memory cell during the programming process.
10. The method of claim 9 , wherein each program-verify cycle comprises verifying that a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.
11. The method of claim 9 , wherein each program-verify cycle comprises:
applying a first voltage to one of the erase gate and the control gate of the selected non-volatile memory cell;
measuring a first current that results through the selected non-volatile memory cell;
applying a second voltage to the one of the erase gate and the control gate of the selected non-volatile memory cell;
measuring a second current that results through the selected non-volatile memory cell;
determining a slope value based on the first voltage, the second voltage, the first current, and the second current;
determining a next programming voltage of the programming voltages of increasing and decreasing magnitude, respectively, based on the slope value;
programming the non-volatile memory cell with the next programming voltage;
repeating the steps of determining a next programming voltage and programming the non-volatile memory cell with the next programming voltage until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a first threshold current value.
12. The method of claim 9 , further comprising:
performing a second programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a second threshold current value.
13. The method of claim 12 , further comprising:
performing a third programming process until a current through the selected non-volatile memory cell during a read or verify operation is less than or equal to a fourth threshold current value.
14. The method of claim 9 , wherein the step of performing a first programming process further comprises:
when a current through the selected non-volatile memory cell is less than or equal to a third threshold current value, erasing the selected non-volatile memory cell and repeating the first programming process.
15. A method of programming a selected non-volatile memory cell to store one of N possible values, where N is an integer greater than 2, the selected non-volatile memory cell comprising a first gate, a first terminal, and a second terminal, the method comprising:
performing a plurality of program-verify cycles on a selected split-gate memory cell comprising a source line terminal, a control gate terminal, and a floating gate, wherein during each of the program-verify cycles a first programming voltage is applied to the source line terminal and the first programming voltage decreases with each subsequent cycle and a second programming voltage is applied to the control gate terminal and the second programming voltage increases with each subsequent cycle.