A reception-side IC chip ( 1 a ) includes a pad ( 15 ) which is connected to a transmission line ( 2 ) which is outside the chip and has a characteristic impedance Z0 of 50Ω, a signal line ( 16 ), one end of which is connected to the pad ( 15 ), a reception-side input unit circuit ( 10 ) configured to receive a signal (S) transmitted from a transmission-side IC chip via the transmission line ( 2 ), a 50-Ω termination resistor ( 11 ), for impedance matching, which is connected between a predetermined voltage and the other end of the signal line ( 16 ) and is configured to terminate the transmission line ( 2 ), and a capacitor ( 12 ) inserted between a node (A) of the signal line ( 16 ) and the termination resistor ( 11 ) and an input terminal (In) of the reception-side input unit circuit ( 10 ). A DC-blocking circuit is formed by the capacitor ( 12 ).
1. An IC chip comprising:
a pad connected to a first transmission line outside the chip;
a signal line, one end of which is connected to the pad;
a termination resistor connected to the other end of the signal line, having a same characteristic impedance as a characteristic impedance of the first transmission line and configured to terminate the first transmission line;
a reception-side input unit circuit configured to receive a signal transmitted from a transmission-side via the first transmission line; and
a capacitor inserted between a node of the signal line and the termination resistor and an input terminal of the reception-side input unit circuit.
2. An IC chip comprising:
a pad connected to a first transmission line outside the chip;
a signal line, one end of which is connected to the pad;
a termination resistor connected to the other end of the signal line and configured to terminate the first transmission line,
a reception-side input unit circuit configured to receive a si anal transmitted from a transmission-side via the first transmission line; and
a capacitor inserted between a node of the signal line and the termination resistor and an input terminal of the reception-side input unit circuit,
wherein a length from the node of the signal line and the termination resistor to the input terminal of the reception-side input unit circuit is shorter than a wavelength of a maximum frequency component of a signal handled by the reception-side input unit circuit.
3. The IC chip according to claim 2 , wherein the capacitor and an input impedance of the reception-side input unit circuit form a high-pass filter, and
the input impedance of the reception-side input unit circuit is set so that a cutoff frequency of the high-pass filter and a capacitance of the capacitor become desired values, respectively.
4. The IC chip according to claim 2 , further comprising:
a bias application circuit configured to apply a DC bias voltage to the input terminal of the reception-side input unit circuit.
5. The IC chip according to claim 4 , wherein a high-pass filter is formed by the capacitor and a combined resistance of an input impedance of the reception-side input unit circuit and an output impedance of the bias application circuit, and
the input impedance of the reception-side input unit circuit and the output impedance of the bias application circuit are set so that a cutoff frequency of the high-pass filter and a capacitance of the capacitor become desired values, respectively.
6. The IC chip according to claim 2 , further comprising:
an inductor inserted in series to the signal line.
7. The IC chip according to claim 2 , further comprising:
a second transmission line inserted in series to the signal line, the second transmission line having a characteristic impedance of not less than 50Ω.
8. An IC chip comprising:
a pad connected to a first transmission line outside the chip;
a signal line, one end of which is connected to the pad;
a termination resistor connected to the other end of the signal line and configured to terminate the first transmission line;
a reception-side input unit circuit configured to receive a signal transmitted from a transmission-side via the first transmission line;
a capacitor inserted between a node of the signal line and the termination resistor and an input terminal of the reception-side input unit circuit, and
a second transmission line inserted in series to the signal line, the second transmission line having a characteristic impedance of not less than 50Ω.
9. The IC chip according to claim 8 , further comprising:
a first inductor inserted in series to the signal line between the pad and the second transmission line; and
a second inductor inserted in series to the signal line between the second transmission line and the node of the signal line and the termination resistor.
10. The IC chip according to claim 9 , wherein the second transmission line includes two transmission lines which are connected in series, and
the IC chip further comprises an electrostatic discharge protection circuit which is connected to a signal line between the two transmission lines.
11. An IC chip comprising:
a pad connected to a first transmission line outside the chip;
a signal line, one end of which is connected to the pad;
a termination resistor connected to the other end of the signal line and configured to terminate the first transmission line;
a reception-side input unit circuit configured to receive a signal transmitted from a transmission-side via the first transmission line;
a capacitor inserted between a node of the signal line and the termination resistor and an input terminal of the reception-side input unit circuit; and
a bias application circuit configured to apply a DC bias voltage to the input terminal of the reception-side input unit circuit, wherein
a high-pass filter is formed by the capacitor and a combined resistance of an input impedance of the reception-side input unit circuit and an output impedance of the bias application circuit, and
the input impedance of the reception-side input unit circuit and the output impedance of the bias application circuit are set so that a cutoff frequency of the high-pass filter and a capacitance of the capacitor become desired values, respectively.
12. The IC chip according to claim 11 , further comprising:
an inductor inserted in series to the signal line.
13. The IC chip according to claim 11 , further comprising:
a second transmission line inserted in series to the signal line, the second transmission line having a characteristic impedance of not less than 50Ω.