IP Library › Granted Patent US 12,278,625
Granted Patent B2
US 12,278,625 · App. 18/005,938 · Granted Apr 15, 2025

Driver circuit

Inventors: Teruo Jo (Tokyo, JP); Munehiko Nagatani (Tokyo, JP); Hideyuki Nosaka (Tokyo, JP)
Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
H03K17/687H02H9/042H03F1/56H03F3/45179H03K17/08142
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Quick Facts
Patent No.
US 12,278,625
App. No.
18/005,938
Granted
Apr 15, 2025
Kind
B2
Abstract

The driver circuit includes DC cut capacitors, an input buffer, input termination resistors connected in series between differential input signal terminals and an ESD protection circuit connected to a connection point of the input terminal resistors. The ESD protection circuit includes diodes.

Claims (55)

1. A driver circuit comprising:

a first input signal terminal;

a second input signal terminal;

an Electro-Static Discharge protection circuit connected to the first input signal terminal and the second input signal terminal;

a first capacitor and a second capacitor each having a first end connected to the Electro-Static Discharge protection circuit; and

an input buffer having a first input terminal and an inverting input terminal, the first input terminal of the input buffer being connected to a second end of the first capacitor and the inverting input terminal connected to a second end of the second capacitor of the input buffer, wherein the Electro-Static Discharge protection circuit includes:

a plurality of first diodes each having a cathode connected to a power supply voltage;

a plurality of second diodes each having anodes connected to ground;

a first transmission line having an input end connected to the first input signal terminal and an output end connected to the first end of the first capacitor;

a second transmission line having an input end connected to the second input signal terminal and an output end connected to the first end of the second capacitor;

a plurality of first input termination resistors arranged along the first transmission line and having a first end connected to the first transmission line; and

a plurality of second input termination resistors arranged along the second transmission line and having a first end connected to the second transmission line and a second end connected to a second end of the first input termination resistor.

2. The driver circuit according to claim 1 , wherein:

the plurality of first input termination resistors is connected in series with the plurality of second input termination resistors with a one-to-one correspondence to provide a plurality of pairs of input termination resistors;

a first diode of the plurality of first diodes is provided for each of the plurality of pairs of input termination resistors, and each of the plurality of first diodes has an anode connected to a connection point of a corresponding first input termination resistor of the plurality of first input termination resistors and a corresponding second input termination resistor of the plurality of second input termination resistors; and

a second diode of the plurality of second diodes is provided for each of the plurality of first diodes, and each of the plurality of second diodes has a cathode connected to an anode of a corresponding first diode of the plurality of first diodes.

3. The driver circuit according to claim 1 , wherein:

the plurality of first input termination resistors is arranged along the first transmission line and has a first end connected to the first transmission line;

the plurality of second input termination resistors is arranged along the second transmission line and has a first end connected to the second transmission line and a second end connected to a second end of the plurality of first input termination resistors;

the plurality of first input termination resistors is connected in series with the plurality of second input termination resistors with a one-to-one correspondence to provide a plurality of pairs of input termination resistors;

a first diode of the plurality of first diodes is provided for every other pair of the plurality of pairs of input termination resistors, and each of the plurality of first diodes has an anode connected to a connection point of a corresponding first input termination resistor of the plurality of first input termination resistors and a corresponding second input termination resistor of the plurality of second input termination resistors; and

each of the plurality of second diodes has an anode connected to a connection point of a corresponding first input termination resistor of the plurality of first input termination resistors and a corresponding second input termination resistor of the plurality of second input termination resistors that are not connected to the plurality of first diodes.

4. A driver circuit comprising:

a first output signal terminal;

a second output signal terminal;

an output circuit having a first output terminal connected to the first output signal terminal and a second output terminal connected to the second output signal terminal;

a first Electro-Static Discharge protection circuit connected to the first output signal terminal and the second output signal terminal, wherein the output circuit includes:

a first transistor and a second transistor each having a base terminal to which a differential signal is input;

a third transistor having a collector terminal connected to the first output signal terminal and an emitter terminal connected to a collector terminal of the first transistor; and

a fourth transistor having a collector terminal connected to the second output signal terminal and an emitter terminal connected to the collector terminal of the second transistor; and

a second Electro-Static Discharge protection circuit connected to a base terminal of the third transistor and a base terminal of the fourth transistor, wherein the second Electro-Static Discharge protection circuit includes:

a first diode having an anode connected to ground and a cathode connected to the base terminal of the third transistor; and

a second diode having an anode connected to ground and a cathode connected to the base terminal of the fourth transistor.

5. The driver circuit according to claim 4 , wherein the first Electro-Static Discharge protection circuit includes:

a third diode having an anode connected to the first output signal terminal and a cathode connected to a power supply voltage; and

a fourth diode having an anode connected to the second output signal terminal and a cathode connected to the power supply voltage.

6. The driver circuit according to claim 5 , wherein the output circuit includes:

the first transistor having a base terminal connected to a non-inverting input terminal of the output circuit;

the second transistor having a base terminal connected to an inverting input terminal of the output circuit;

the third transistor having a base terminal connected to a first bias voltage, a collector terminal connected to the first output signal terminal, and an emitter terminal connected to a collector terminal of the first transistor;

the fourth transistor having a base terminal connected to the first bias voltage, a collector terminal connected to the second output signal terminal, and an emitter terminal connected to a collector terminal of the second transistor;

a fifth transistor having a base terminal connected to a second bias voltage, a collector terminal connected to emitter terminals of the first and second transistors, and an emitter terminal connected to ground; and

the second Electro-Static Discharge protection circuit.

7. The driver circuit according to claim 4 , wherein the first Electro-Static Discharge protection circuit is arranged between the first output signal terminal and the second output signal terminal, and includes:

a first transmission line having an input end connected to a non-inverted output terminal and an output terminal connected to the first output signal terminal of the output circuit;

a second transmission line having an input end connected to an inverted output terminal and an output end connected to the second output signal terminal of the output circuit;

a plurality of third diodes arranged along the first transmission line and having anodes connected to the first transmission line and having cathodes connected to a power supply voltage; and

a plurality of second diodes arranged along the second transmission line and having anodes connected to the second transmission line and having cathodes connected to the power supply voltage.

8. The driver circuit according to claim 7 , wherein the output circuit includes:

the first transistor having a base terminal connected to a non-inverted input terminal of the output circuit;

the second transistor having a base terminal connected to an inverted input terminal of the output circuit;

the third transistor having a base terminal connected to a first bias voltage, a collector terminal connected to the first output signal terminal, and an emitter terminal connected to a collector terminal of the first transistor;

the fourth transistor having a base terminal connected to the first bias voltage, a collector terminal connected to the second output signal terminal, and an emitter terminal connected to a collector terminal of the second transistor;

a fifth transistor having a base terminal connected to a second bias voltage, a collector terminal connected to emitter terminals of the first and second transistors, and an emitter terminal connected to ground; and

the second Electro-Static Discharge protection circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2023
From: JO, TERUO; NAGATANI, MUNEHIKO; NOSAKA, HIDEYUKI
To: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Reel/Frame 062414/0101 →
Continuity (1)
Related Publication 20230275581A1 · Aug 31, 2023
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