IP Library Granted Patent US 11,775,045
Granted Patent B2
US 11,775,045 · App. 16/781,227 · Granted Oct 3, 2023

Managing power at a station via a physical layer device and related systems, methods and devices

Inventors: William T. Baggett (Austin, TX); Venkatraman Iyer (Austin, TX)
Assignee: Microchip Technology Incorporated
G06F1/3234G06F13/20G06F2213/40
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Quick Facts
Patent No.
US 11,775,045
App. No.
16/781,227
Granted
Oct 3, 2023
Kind
B2
Abstract

Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.

Claims (67)

1. An apparatus, comprising:

transmission/reception circuitry associated with an interruptible power domain;

a core logic associated with the interruptible power domain to perform one or more operations of a physical layer device for interfacing with a shared bus; and

a power management logic associated with an uninterruptable power domain to enable and disable supply of power to the interruptible power domain,

wherein the transmission/reception circuitry and the core logic respectively exhibit states responsive to a state of supply of power to the interruptible power domain, the states including an unpowered state responsive to a disabled supply of power to the interruptible power domain and a powered states responsive to an enabled supply of power to the interruptible power domain.

2. The apparatus of claim 1 , comprising:

an input; and

a sensing circuitry to detect a wakeup signal asserted at the input, the power management logic to enable the supply of power to the interruptible power domain responsive to detection of the detected asserted wakeup signal by said sensing circuitry.

3. The apparatus of claim 1 , wherein the power management logic to enable the supply of power to the interruptible power domain in response to one or more of:

a valid wakeup signal; and

a valid bus activity.

4. The apparatus of claim 1 , wherein the power management logic to disable the supply of power to the interruptible power domain responsive to one or more of:

a sleep control signal;

an inactive input assigned to receive a wakeup signal; and

an inactive bus.

5. The apparatus of claim 1 , wherein the core logic to assert a wakeup signal at an output of the physical layer device in response to waking up from a sleep mode.

6. The apparatus of claim 2 , comprising:

an energy detection circuitry to detect bus activity, the power management logic to enable the supply of power to the interruptible power domain responsive to detection by said energy detection circuitry of a valid bus activity.

7. A system, comprising:

a first station controller; and

a first physical layer device to interface the first station controller with a shared bus of a network segment and to enable and disable a supply of power to the first station controller and to an interruptible power domain of the first physical layer device.

8. The system of claim 7 , wherein the first physical layer device comprises:

a power management logic associated with an uninterruptable power domain of the first physical layer device to enable and disable the supply of the power to the first station controller.

9. The system of claim 7 , comprising equipment, the network segment to operatively couple the equipment to a network.

10. The system of claim 7 , comprising:

a second station controller; and

a second physical layer device of the network segment to enable supply of power to the second station controller responsive to a wakeup signal received from the first physical layer device.

11. The system of claim 8 , wherein the first physical layer device comprises:

a core logic associated with the interruptible power domain of the first physical layer device.

12. The system of claim 9 , comprising:

a switch to provide an interruptible path for supplying power to the equipment.

13. The system of claim 11 , wherein the power management logic to disable the supply of power to the first station controller responsive to a sleep control signal provided by the core logic.

14. The system of claim 12 , comprising:

a power master to generate power control signals for the network, the power control signals comprising instructions to selectively reset stations of respective network segments of the network.

15. The system of claim 12 , comprising:

a power master to generate power control signals for the network, the power control signals comprising instructions to force stations of respective network segments of the network to enter a sleep mode.

16. The system of claim 13 , comprising:

a control bus, the first physical layer device and the first station controller operatively coupled via the control bus to

provide the sleep control signal to the power management logic.

17. The system of claim 14 , wherein the instructions to selectively reset stations of the respective network segments of the network comprising instructions to enter a sleep mode.

18. The system of claim 15 , wherein the instructions comprise an assertion of a power control signal at the shared bus.

19. The system of claim 18 , wherein the assertion of the power control signal exhibits an energy level different than an energy level associated with communication messages conveyed over the network segment.

20. A method, comprising:

disabling a supply of power to a first power domain of a station in response to an asserted signal, the signal asserted by a physical layer device of the station responsive to:

receiving a sleep control signal; or

observing a signal indicative of bus inactivity at a shared bus,

wherein the first power domain of the station includes:

a transmission/reception circuitry of the physical layer device, and

a core logic of the physical layer device,

wherein the transmission/reception circuitry and the core logic respectively exhibit states responsive to a state of supply of power to the first power domain, the states including an unpowered state responsive to a disabled supply of power to the first power domain and a powered state responsive to an enabled supply of power to the first power domain; and

continuing to supply power to a second power domain of the station while the supply of power to the first power domain of the station is disabled.

21. The method of claim 20 , wherein disabling the supply of power to the first power domain of the station in response to the received sleep control signal or the observed signal indicative of bus inactivity at the shared bus comprises:

de-asserting an enablement signal thereby indicating that power should not be supplied to the first power domain of the station responsive to:

the received sleep control signal; or

the observed signal indicative of bus inactivity at the shared bus.

22. The method of claim 20 , wherein the observing the signal indicative of bus inactivity comprises observing an energy level of the signal and determining that the energy level is different than an energy level associated with a valid communication signal.

23. The method of claim 20 , comprising:

supplying power to the first power domain of the station responsive to:

observing a wakeup signal at an input of the physical layer device of the station; or

observing a signal indicative of valid bus activity at the shared bus.

24. The method of claim 23 , comprising:

asserting an enablement signal thereby indicating that power should be supplied to the first power domain of the station responsive to:

the observed wakeup signal; or

the observed signal indicative of valid bus activity at the shared bus; and

starting the supplying of the power to the first power domain of the station responsive to the asserted enablement signal.

25. The method of claim 23 , comprising:

asserting a second wakeup signal at an output of the physical layer device in response to supplying power to the first power domain, the output being operably coupled to an input of another physical layer device.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 064120 FRAME: 0600. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 13, 2023
From: BAGGETT, WILLIAM T.; IYER, VENKATRAMAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 064272/0007 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND INVENTORS NAME PREVIOUSLY RECORDED ON REEL 051716 FRAME 0701. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 21, 2023
From: BAGGETT, WILLIAM T.; IYER, VENKATRAMAN
To: MICROCHIP TECHNOLOGY INCORORATED
Reel/Frame 064120/0600 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: BAGGETT, WILLIAM T.; IYER, VENKAT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 051716/0701 →
Continuity (2)
Provisional Application 62861226 · Jun 13, 2019
Related Publication 20200393891A1 · Dec 17, 2020