Four gate, split-gate flash memory array with byte erase operation
A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.
1. A memory device, comprising:
a plurality of memory cells configured in rows and columns on a semiconductor substrate, wherein each of the memory cells includes:
source and drain regions formed in the substrate and defining a channel region of the substrate extending there between,
a floating gate disposed vertically over and insulated from a first portion of the channel region,
a select gate disposed vertically over and insulated from a second portion of the channel region,
a control gate disposed vertically over and insulated from the floating gate, and
an erase gate disposed vertically over and insulated from the source region;
a plurality of word lines each electrically directly connecting together all of the select gates for one of the rows of the memory cells;
a plurality of control gate lines each electrically directly connecting together all of the control gates for one of the rows of the memory cells;
a plurality of bit lines each electrically directly connecting together all of the drain regions for one of the columns;
a plurality of first sub source lines each electrically directly connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns;
a plurality of second sub source lines each electrically directly connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns, wherein the first plurality of the columns is different from the second plurality of the columns;
a first erase gate line electrically directly connecting together all of the erase gates of the memory cells in the first plurality of the columns;
a second erase gate line electrically directly connecting together all of the erase gates of the memory cells in the second plurality of the columns;
a plurality of source lines;
a plurality of first select transistors each connected between one of first sub source lines and one of the source lines;
a plurality of second select transistors each connected between one of second sub source lines and one of the source lines;
a first select transistor line connected to gates of the first select transistors; and
a second select transistor line connected to gates of the second select transistors.
2. The memory device of claim 1 , wherein for each of the source lines, one of the first select transistors connected thereto is connected to one of the first sub source lines for a first row of the memory cells and one of the second select transistors connected thereto is connected to one of the second sub source lines for the first row of the memory cells.
3. The memory device of claim 1 , further comprising:
a controller configured to perform an erase operation on a target group of the memory cells which are in the first plurality of the columns and are connected to a first of the control gate lines, by:
applying a positive voltage to the first erase gate line;
applying a zero voltage or a negative voltage to the first control gate line; and
applying a positive voltage to all of the control gate lines except the first control gate line.
4. The memory device of claim 3 , wherein the controller is configured to perform the erase operation further by applying a zero voltage or a voltage below a threshold voltage of the first select transistors to the first select transistor line.
5. The memory device of claim 4 , wherein the controller is configured to perform the erase operation further by applying a zero voltage to the second select transistor line.
6. The memory device of claim 1 , further comprising:
a controller configured to perform a program operation on one of the memory cells in the first plurality of the columns, wherein the one memory cell is connected to a first of the word lines, and a first of the control gate lines, by:
applying a positive voltage to the first word line;
applying a positive voltage to the first control gate line;
applying a positive voltage to the first erase gate line; and
applying a positive voltage to the first select transistor line.
7. The memory device of claim 6 , wherein the controller is configured to perform the program operation further by applying a zero voltage to the second select transistor line.
8. The memory device of claim 1 , wherein:
each of the first sub source lines electrically directly connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the first plurality of the columns; and
each of the second sub source lines electrically directly connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the second plurality of the columns.
9. The memory device of claim 1 , wherein:
for each one of the first sub source lines, all of the source regions electrically directly connected together by the one first sub source line are for memory cells in only one of the rows of the memory cells; and
for each one of the second sub source lines, all of the source regions electrically directly connected together by the one second sub source line are for memory cells in only one of the rows of the memory cells.
10. A memory device, comprising:
a plurality of memory cells configured in alternating even and odd rows, and in columns, on a semiconductor substrate, wherein each of the memory cells includes:
source and drain regions formed in the substrate and defining a channel region of the substrate extending there between,
a floating gate disposed vertically over and insulated from a first portion of the channel region,
a select gate disposed vertically over and insulated from a second portion of the channel region,
a control gate disposed vertically over and insulated from the floating gate, and
an erase gate disposed vertically over and insulated from the source region;
a plurality of word lines each electrically directly connecting together all of the select gates for one of the rows of the memory cells;
a plurality of control gate lines each electrically directly connecting together all of the control gates for one of the rows of the memory cells;
a plurality of bit lines each electrically directly connecting together all of the drain regions for one of the columns;
a plurality of first sub source lines each electrically directly connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a first plurality of the columns;
a plurality of second sub source lines each electrically directly connecting together the source regions of the memory cells that are in one of the rows of the memory cells and are in a second plurality of the columns, wherein the first plurality of the columns is different from the second plurality of the columns;
a first erase gate line electrically directly connecting together all of the erase gates of the memory cells that are in the even rows of the memory cells and are in the first plurality of the columns;
a second erase gate line electrically directly connecting together all of the erase gates of the memory cells that are in the odd rows of the memory cells and are in the first plurality of the columns;
a third erase gate line electrically directly connecting together all of the erase gates of the memory cells that are in the even rows of the memory cells and are in the second plurality of the columns;
a fourth erase gate line electrically directly connecting together all of the erase gates of the memory cells that are in the odd rows of the memory cells and are in the second plurality of the columns;
a plurality of source lines;
a plurality of first select transistors each connected between one of first sub source lines and one of the source lines;
a plurality of second select transistors each connected between one of second sub source lines and one of the source lines;
a first select transistor line connected to gates of the first select transistors; and
a second select transistor line connected to gates of the second select transistors.
11. The memory device of claim 10 , wherein for each of the source lines, one of the first select transistors connected thereto is connected to one of the first sub source lines for a first one of the rows of the memory cells and one of the second select transistors connected thereto is connected to one of the second sub source lines for the first one of rows of the memory cells.
12. The memory device of claim 10 , further comprising:
a controller configured to perform an erase operation on a target group of the memory cells which are in the first plurality of the columns, are connected to a first of the control gate lines, and are connected to the second erase gate line, by:
applying a positive voltage to the second erase gate line;
applying a zero voltage or a negative voltage to the first control gate line;
applying a positive voltage to all of the control gate lines that are connected to the memory cells which are also connected to the second erase gate line except the first control gate line.
13. The memory device of claim 12 , wherein the controller is configured to perform the erase operation further by applying a zero voltage to all the control gate lines that are connected to the memory cells which are also connected to the first erase gate line.
14. The memory device of claim 12 , wherein the controller is configured to perform the erase operation further by applying a low positive voltage to all the control gate lines that are connected to the memory cells which are also connected to the first erase gate line, where the low positive voltage is less than the positive voltage applied to all of the control gate lines that are connected to the memory cells which are also connected to the second erase gate line except the first control gate line.
15. The memory device of claim 12 , wherein the controller is configured to perform the erase operation further by applying a zero voltage or a voltage below a threshold voltage of the first select transistors to the first select transistor line.
16. The memory device of claim 15 , wherein the controller is configured to perform the erase operation further by applying a zero voltage to the second select transistor line.
17. The memory device of claim 10 , further comprising:
a controller configured to perform a program operation on one of the memory cells in the first plurality of the columns, wherein the one memory cell is connected to a first of the word lines, to the second erase gate line, and a first of the control gate lines, by:
applying a positive voltage to the first word line;
applying a positive voltage to the first control gate line;
applying a positive voltage to the second erase gate line; and
applying a positive voltage to the first select transistor line.
18. The memory device of claim 17 , wherein the controller is configured to perform the program operation further by applying a zero voltage to the second select transistor line.
19. The memory device of claim 10 , wherein:
each of the first sub source lines electrically directly connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the first plurality of the columns; and
each of the second sub source lines electrically directly connects together the source regions of the memory cells that are in a second one of the rows of the memory cells and that are in the second plurality of the columns.
20. The memory device of claim 10 , wherein:
for each one of the first sub source lines, all of the source regions electrically directly connected together by the one first sub source line are for memory cells in only one of the rows of the memory cells; and
for each one of the second sub source lines, all of the source regions electrically directly connected together by the one second sub source line are for memory cells in only one of the rows of the memory cells.