Integrated circuit devices and methods of manufacturing the same
An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.
1. An integrated circuit device comprising a capacitor structure, wherein the capacitor structure comprises:
a bottom electrode over a substrate;
a supporter on a sidewall of the bottom electrode;
a dielectric layer on the bottom electrode and the supporter; and
a top electrode on the dielectric layer and covering the bottom electrode,
wherein the bottom electrode comprises:
a base electrode layer comprising niobium nitride and extending in a first direction that is perpendicular to a top surface of the substrate;
a first seed layer surrounded by the supporter and in contact with at least a portion of the base electrode layer; and
a second seed layer between a bottom surface of the base electrode layer and the substrate, and
wherein each of the first seed layer and the second seed layer comprises titanium nitride or tungsten.
2. The integrated circuit device of claim 1 , wherein the base electrode layer comprises a first sidewall and a second sidewall, wherein the first sidewall of the base electrode layer is surrounded by the first seed layer, and wherein the second sidewall of the base electrode layer is surrounded by the dielectric layer.
3. The integrated circuit device of claim 2 , wherein the first sidewall and the second sidewall of the base electrode layer are coplanar.
4. The integrated circuit device of claim 2 , wherein the base electrode layer is isolated from the supporter, and wherein the first seed layer is between the first sidewall of the base electrode layer and a sidewall of the supporter.
5. The integrated circuit device of claim 1 , wherein the base electrode layer comprises a first base electrode layer; and a second base electrode layer over the first base electrode layer and spaced apart from the first base electrode layer in the first direction,
wherein the first seed layer is between the first base electrode layer and the second base electrode layer;
wherein a third seed layer is on a sidewall of the second base electrode layer and surrounded by the supporter, and
wherein the third seed layer comprises titanium nitride or tungsten.
6. The integrated circuit device of claim 5 , wherein the second base electrode layer comprises a first sidewall and a second sidewall, wherein the first base electrode layer comprises a third sidewall, wherein the first sidewall of the second base electrode layer is surrounded by the first seed layer, and wherein the second sidewall of the second base electrode layer and the third sidewall of the first base electrode layer are surrounded by the dielectric layer.
7. The integrated circuit device of claim 6 , wherein the first sidewall and the second sidewall of the second base electrode layer are coplanar, and wherein the first sidewall of the second base electrode layer is recessed inwards with respect to the third sidewall of the first base electrode layer.
8. The integrated circuit device of claim 6 , wherein the first base electrode layer and the second base electrode layer are isolated from the supporter, and wherein the first seed layer is between the first sidewall of the second base electrode layer and a sidewall of the supporter.
9. The integrated circuit device of claim 6 , wherein the third sidewall of the first base electrode layer is coplanar with a sidewall of the supporter.
10. The integrated circuit device of claim 1 , wherein a portion of the dielectric layer in contact with the base electrode layer comprises hafnium oxide having a tetragonal crystal phase.
11. An integrated circuit device comprising a capacitor structure, wherein the capacitor structure comprises:
a landing pad over a substrate;
a bottom electrode comprising a bottom surface in contact with a top surface of the landing pad;
a supporter on a sidewall of the bottom electrode;
a dielectric layer on the bottom electrode and the supporter; and
a top electrode on the dielectric layer to cover the bottom electrode,
wherein the bottom electrode comprises a base electrode layer comprising niobium nitride and extending in a first direction that is perpendicular to a top surface of the substrate, and
wherein a portion of the dielectric layer in contact with the base electrode layer comprises hafnium oxide having a tetragonal crystal phase.
12. The integrated circuit device of claim 11 , wherein the base electrode layer is free of seams and voids.
13. The integrated circuit device of claim 11 , wherein the base electrode layer comprises a first sidewall and a second sidewall, wherein the first sidewall of the base electrode layer is surrounded by the supporter, wherein the second sidewall of the base electrode layer is surrounded by the dielectric layer, and wherein the first sidewall and the second sidewall of the base electrode layer are coplanar.
14. An integrated circuit device comprising a capacitor structure, wherein the capacitor structure comprises:
a bottom electrode over a substrate;
a supporter on a sidewall of the bottom electrode;
a dielectric layer on the bottom electrode and the supporter; and
a top electrode on the dielectric layer and covering the bottom electrode,
wherein the bottom electrode comprises:
a first base electrode layer comprising niobium nitride and extending in a first direction that is perpendicular to a top surface of the substrate;
a second base electrode layer over the first base electrode layer and spaced apart from the first base electrode layer in the first direction; and
a seed layer between the first base electrode layer and the second base electrode layer, the seed layer surrounded by the supporter and having a first sidewall coplanar with the dielectric layer and coplanar with the first base electrode layer.
15. The integrated circuit device of claim 14 , wherein the second base electrode layer comprises a first sidewall and a second sidewall, wherein the first sidewall of the second base electrode layer is surrounded by the seed layer, and wherein the second sidewall of the second base electrode layer is surrounded by the dielectric layer.
16. The integrated circuit device of claim 15 , wherein the first sidewall and the second sidewall of the second base electrode layer are coplanar.
17. The integrated circuit device of claim 14 , wherein the seed layer is a second seed layer, the integrated circuit device further comprising a first seed layer between a bottom surface of the first base electrode layer and the substrate.
18. The integrated circuit device of claim 17 , further comprising a landing pad, wherein the first seed layer is between the bottom surface of the first base electrode layer and the landing pad.