Granted Patent B2

US 11,017,866 · App. 16/803,401 · Granted May 25, 2021

Abstract

Claims (31)

1. A method of improving stability of a memory device that includes a plurality of non-volatile memory cells and a controller configured to program each of the memory cells within a range of programming states bounded by a minimum program state and a maximum program state, the method comprising:

testing the memory cells to confirm the memory cells are operational;

programming each of the memory cells to a mid-program state; and

baking the memory device at a high temperature while the memory cells are programmed to the mid-program state;

wherein, for each of the memory cells:

the memory cell has a first threshold voltage when programmed in the minimum program state,

the memory cell has a second threshold voltage when programmed in the maximum program state, and

the memory cell has a third threshold voltage when programmed in the mid-program state,

wherein the third threshold voltage is substantially at a mid-point between the first and second threshold voltages;

wherein each of the memory cells comprises:

spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between,

a floating gate disposed vertically over and insulated from a first portion of the channel region,

a select gate disposed vertically over and insulated from a second portion of the channel region, and

a control gate disposed vertically over and insulated from the floating gate.

2. The method of claim 1 , wherein each of the memory cells further comprises:

an erase gate disposed over and insulated from the source region.

3. A method of improving stability of a memory device that includes a plurality of non-volatile memory cells each including at least a floating gate disposed over and insulated from a channel region of a semiconductor substrate and a control gate disposed over and insulated from the floating gate, and a controller configured to program each of the memory cells within a range of programming states bounded by a minimum program state and a maximum program state, and to read each of the memory cells using a read voltage applied to the control gate, the method comprising:

testing the memory cells to confirm the memory cells are operational;

programming each of the memory cells to a mid-program state; and

baking the memory device at a high temperature while the memory cells are programmed to the mid-program state;

wherein, for each of the memory cells:

the memory cell produces a first read current during a read operation using the read voltage applied to the control gate when programmed in the minimum program state,

the memory cell produces a second read current during a read operation using the read voltage applied to the control gate when programmed in the maximum program state, and

the memory cell produces a third read current during a read operation using the read voltage applied to the control gate when programmed in the mid-program state,

wherein the third read current is substantially at a logarithmic mid-point between the first and second read currents.

4. The method of claim 3 , wherein each of the memory cells comprises:

spaced apart source and drain regions formed in a semiconductor substrate, with the channel region of the substrate extending there between,

the floating gate is disposed vertically over and insulated from a first portion of the channel region,

a select gate disposed vertically over and insulated from a second portion of the channel region.

5. The method of claim 4 , wherein each of the memory cells further comprises:

an erase gate disposed over and insulated from the source region.

Assignments (13)