Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
1. A semiconductor memory device comprising:
a plurality of semiconductor memory cells connected in series, wherein at least two of said memory cells each include:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
wherein said floating body region is configured to store data as charge therein to define a state of said memory cell selected from at least first and second states;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein at least one of said first bipolar device or second bipolar device maintains a state of said memory cell;
wherein said transistor is usable to access said memory cell; and
wherein current flow through said memory cell is larger when said memory cell is in one of said at least first and second states than when said memory cell is in another of said at least first and second states.
2. The semiconductor memory device of claim 1 , wherein a voltage bias is applied to said first and second collectors to maintain a state of said memory cell.
3. The semiconductor memory device of claim 2 , wherein said voltage bias is a constant positive voltage bias.
4. The semiconductor memory device of claim 2 , wherein said voltage bias is a periodic pulse of positive voltage bias.
5. The semiconductor memory device of claim 1 , wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, and wherein said first collector and said second collector have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.
6. The semiconductor memory device of claim 5 , wherein said at least two memory cells each further comprise a substrate having said first conductivity type.
7. The semiconductor memory device of claim 1 , wherein application of voltage to at least one of said first and second collectors of first and second memory cells of said at least two of said memory cells maintains said first and second memory cells in said states.
8. The semiconductor memory device of claim 1 , wherein said semiconductor memory device is formed in a fin structure.
9. A semiconductor memory array comprising:
a plurality of links or strings of semiconductor memory cells, wherein each of said semiconductor memory cells includes:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
wherein said floating body region is configured to store data as charge therein to define a state of said memory cell selected from at least first and second states;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein at least one of said first bipolar device or said second bipolar device maintains a state of said memory cell;
wherein said transistor is usable to access said memory cell;
wherein current flow through said memory cell is larger when said memory cell is in one of said at least first and second states than when said memory cell is in another of said at least first and second states; and
wherein said collectors are commonly connected to at least two of said semiconductor memory cells.
10. The semiconductor memory array of claim 9 , wherein a voltage bias is applied to said first and second collectors to maintain a state of said memory cell.
11. The semiconductor memory array of claim 10 , wherein said voltage bias is a constant positive voltage bias.
12. The semiconductor memory array of claim 10 , wherein said voltage bias is a periodic pulse of positive voltage bias.
13. The semiconductor memory array of claim 9 , wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, and wherein said first collector and said second collector have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.
14. The semiconductor memory array of claim 13 , wherein said at least two memory cells each further comprise a substrate having said first conductivity type.
15. The semiconductor memory array of claim 9 , wherein application of voltage to at least one of said first and second collectors of first and second memory cells of said at least two of said memory cells maintains said first and second memory cells in said states.
16. The semiconductor memory array of claim 9 , wherein said link or string of semiconductor memory cells is formed in a fin structure.
17. An integrated circuit comprising:
a plurality of links or strings of semiconductor memory cells, wherein each said semiconductor memory cell includes:
a transistor comprising a source region, a floating body region, a drain region, and a gate;
wherein said floating body region is configured to store data as charge therein to define a state of said memory cell selected from at least first and second states;
a first bipolar device having a first floating base region, a first emitter, and a first collector; and
a second bipolar device having a second floating base region, a second emitter, and a second collector;
wherein said first floating base region and said second floating base region are common to said floating body region;
wherein said first collector is common to said second collector;
wherein at least one of said first bipolar device or said second bipolar device maintains a state of said memory cell;
wherein said transistor is usable to access said memory cell;
wherein current flow through said memory cell is larger when said memory cell is in one of said at least first and second states than when said memory cell is in another of said at least first and second states;
wherein said collectors are commonly connected to at least two of said semiconductor memory cells; and
a control circuitry configured to apply voltage to said collectors.
18. The integrated circuit of claim 17 , wherein a voltage bias is applied to said first and second collectors to maintain a state of said memory cell.
19. The integrated circuit of claim 18 , wherein said voltage bias is a constant positive voltage bias.
20. The integrated circuit of claim 18 , wherein said voltage bias is a periodic pulse of positive voltage bias.
21. The integrated circuit of claim 17 , wherein said floating body region has a first conductivity type selected from p-type and n-type conductivity types, and wherein said first collector and said second collector have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type.
22. The integrated circuit of claim 21 , wherein said at least two memory cells each further comprise a substrate having said first conductivity type.
23. The integrated circuit of claim 17 , wherein applications of voltage to said collectors maintain said memory cells in their respective states.