IP Library › Granted Patent US 11,222,906
Granted Patent B2
US 11,222,906 · App. 16/809,663 · Granted Jan 11, 2022

Display device, semiconductor device, and driving method thereof

Inventors: Atsushi Umezaki (Kanagawa, JP); Hajime Kimura (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/1225G09G3/20G09G3/3674G09G3/3677G11C19/28G11C19/287H01L27/124H01L29/7869G09G2310/0286
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Quick Facts
Patent No.
US 11,222,906
App. No.
16/809,663
Granted
Jan 11, 2022
Kind
B2
Abstract

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

Claims (62)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor have the same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to a third line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to the third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to the fourth line,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the fourth line, and a gate of the fifth transistor is electrically connected to a fifth line,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to a sixth line,

wherein one of a source and a drain of the seventh transistor is electrically connected to the second line, the other of the source and the drain of the seventh transistor is electrically connected to the third line, and a gate of the seventh transistor is electrically connected to the fifth line,

wherein one of a source and a drain of the eighth transistor is electrically connected to the second line, the other of the source and the drain of the eighth transistor is electrically connected to the third line, and a gate of the eighth transistor is electrically connected to the sixth line,

wherein the second line is configured to be supplied with a signal output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor,

wherein a ratio of a channel width to a channel length of the third transistor is smaller than a ratio of a channel width to a channel length of the fourth transistor,

wherein a ratio of a channel width to a channel length of the sixth transistor is smaller than the ratio of the channel width to the channel length of the fourth transistor, and

wherein a ratio of a channel width to a channel length of the eighth transistor is larger than a ratio of a channel width to a channel length of the second transistor.

2. The semiconductor device according to claim 1 , wherein the first line is configured to be supplied with a first clock signal.

3. The semiconductor device according to claim 1 ,

wherein the first line is configured to be supplied with a first clock signal, and

wherein the fifth line is configured to be supplied with a second clock signal.

4. The semiconductor device according to claim 1 ,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprises an oxide semiconductor including In, Ga, and Zn.

5. The semiconductor device according to claim 1 , wherein an off-state current of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is 1 aA/μm or less.

6. The semiconductor device according to claim 1 , wherein the circuit is included in a shift register of a liquid crystal display device.

7. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor;

an eighth transistor; and

a ninth transistor,

wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor have the same conductivity type,

wherein one of a source and a drain of the first transistor is electrically connected to a first line and the other of the source and the drain of the first transistor is electrically connected to a second line,

wherein one of a source and a drain of the second transistor is electrically connected to the second line and the other of the source and the drain of the second transistor is electrically connected to a third line,

wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to the third line, and a gate of the third transistor is electrically connected to a gate of the second transistor,

wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fourth transistor is electrically connected to a fourth line, and a gate of the fourth transistor is electrically connected to the fourth line,

wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the fifth transistor is electrically connected to the fourth line, and a gate of the fifth transistor is electrically connected to a fifth line,

wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the sixth transistor is electrically connected to the third line, and a gate of the sixth transistor is electrically connected to a sixth line,

wherein one of a source and a drain of the seventh transistor is electrically connected to the second line, the other of the source and the drain of the seventh transistor is electrically connected to the third line, and a gate of the seventh transistor is electrically connected to the fifth line,

wherein one of a source and a drain of the eighth transistor is electrically connected to the second line, the other of the source and the drain of the eighth transistor is electrically connected to the third line, and a gate of the eighth transistor is electrically connected to the sixth line,

wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the ninth transistor is electrically connected to the third line, and a gate of the ninth transistor is electrically connected to the gate of the first transistor,

wherein the second line is configured to be supplied with a signal output from a circuit comprising the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor,

wherein a ratio of a channel width to a channel length of the third transistor is smaller than a ratio of a channel width to a channel length of the fourth transistor,

wherein a ratio of a channel width to a channel length of the sixth transistor is smaller than the ratio of the channel width to the channel length of the fourth transistor, and

wherein a ratio of a channel width to a channel length of the eighth transistor is larger than a ratio of a channel width to a channel length of the second transistor.

8. The semiconductor device according to claim 7 , wherein the first line is configured to be supplied with a first clock signal.

9. The semiconductor device according to claim 7 ,

wherein the first line is configured to be supplied with a first clock signal, and

wherein the fifth line is configured to be supplied with a second clock signal.

10. The semiconductor device according to claim 7 ,

wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor comprises an oxide semiconductor including In, Ga, and Zn.

11. The semiconductor device according to claim 7 , wherein an off-state current of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is 1 aA/μm or less.

12. The semiconductor device according to claim 7 , wherein the circuit is included in a shift register of a liquid crystal display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2020
From: UMEZAKI, ATSUSHI; KIMURA, HAJIME
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 052028/0105 →
Priority Claims (1)
JP 2010-036902 · Feb 23, 2010 · national
Continuity (5)
Continuation 15680348 · Aug 18, 2017
Continuation 14885353 · Oct 16, 2015
Division 14085864 · Nov 21, 2013
Continuation 13025479 · Feb 11, 2011
Related Publication 20200203387A1 · Jun 25, 2020
Cited By (1)
US 12,482,413