Semiconductor memory device and method for manufacturing same
According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.
1. A semiconductor memory device, comprising:
a stacked body including a plurality of insulating layers and a plurality of conductive films, each of the plurality of insulating layers and each of the plurality of conductive films being alternately stacked, a trench being formed in the stacked body, the trench extending in a first direction, and each of the conductive films being divided by the trench;
a plurality of semiconductor pillars provided in the trench and extending in a stacking direction of the insulating layers and the conductive films; and
an insulating member provided in the trench between adjacent of the semiconductor pillars in the first direction, the insulating member including a pair of non-flat surfaces facing a pair of side surfaces of the trench extending along the first direction and a pair of curved surfaces facing the adjacent semiconductor pillars on both sides of the insulating member in the first direction, the curved surfaces each having an arc shape as viewed in the stacking direction, wherein, on the both sides of the insulating member in the first direction, one of the pair of curved surfaces being located at one side in the first direction and the other of the pair of curved surfaces being located at the other side in the first direction with respect to the pair of non-flat surfaces between the adjacent semiconductor pillars,
a pair of memory transistors being provided so as to correspond to regions of each of the semiconductor pillars, the regions facing the pair of side surfaces of the trench, the pair of memory transistors being disposed at an intersection between one of the semiconductor pillars and one of the conductive films.
2. The device according to claim 1 , wherein each of the regions facing the pair of side surfaces of the trench includes a substantially flat side surface parallel to the side surfaces of the trench.
3. The device according to claim 1 , wherein the pair of memory transistors are arranged in a second direction intersecting with the first direction and the stacking direction.
4. The device according to claim 1 , further comprising:
an insulating material provided between the regions of each of the semiconductor pillars and the conductive films.
5. The device according to claim 1 , wherein one of the pair of memory transistors includes a charge trap portion between one region of the regions of each of the semiconductor pillars and one of the conductive films.
6. The device according to claim 5 , wherein the charge trap portion is formed from silicon nitride.
7. The device according to claim 5 , wherein one of the pair of memory transistors further includes a tunnel layer between the charge trap portion and one region of the regions of each of the semiconductor pillars.
8. The device according to claim 7 , wherein the tunnel layer includes silicon and oxygen.
9. The device according to claim 5 , wherein one of the pair of memory transistors further includes a block layer between the charge trap portion and one of the conductive films.
10. The device according to claim 9 , wherein the block layer includes silicon and oxygen.
11. A semiconductor memory device, comprising:
a stacked body including a plurality of insulating layers and a plurality of conductive films, each of the plurality of insulating layers and each of the plurality of conductive films being alternately stacked, a trench being formed in the stacked body, the trench extending in a first direction, and each of the conductive films being divided by the trench;
a plurality of semiconductor pillars provided in the trench and extending in a stacking direction of the insulating layers and the conductive films; and
an insulating member provided between the semiconductor pillars in the trench, the insulating member including a pair of non-flat surfaces facing a pair of side surfaces of the trench extending along the first direction and a pair of curved surfaces facing the semiconductor pillars on both sides in the first direction, the curved surfaces each having an arc shape as viewed in the stacking direction,
a pair of memory transistors being provided so as to correspond to regions of each of the semiconductor pillars, the regions facing the pair of side surfaces of the trench, the pair of memory transistors being disposed at an intersection between one of the semiconductor pillars and one of the conductive films,
wherein each of the regions facing the pair of side surfaces of the trench includes a substantially flat side surface parallel to the side surfaces of the trench.
12. The device according to claim 11 , wherein the pair of memory transistors are arranged in a second direction intersecting with the first direction and the stacking direction.
13. The device according to claim 11 , wherein the insulating member includes a plurality of insulating portions provided at intervals in the first direction in the trench and the semiconductor pillars and the insulating portions are alternately arranged in the first direction in the trench.
14. The device according to claim 11 , further comprising:
an insulating material provided between the regions of each of the semiconductor pillars and the conductive films.
15. The device according to claim 11 , wherein one of the pair of memory transistors includes a charge trap portion between one region of the regions of each of the semiconductor pillars and one of the conductive films.
16. The device according to claim 15 , wherein the charge trap portion is formed from silicon nitride.
17. The device according to claim 15 , wherein one of the pair of memory transistors further includes a tunnel layer between the charge trap portion and one region of the regions of each of the semiconductor pillars.
18. The device according to claim 17 , wherein the tunnel layer includes silicon and oxygen.
19. The device according to claim 15 , wherein one of the pair of memory transistors further includes a block layer between the charge trap portion and one of the conductive films.
20. The device according to claim 19 , wherein the block layer includes silicon and oxygen.