Granted Patent B2

US 11,074,980 · App. 16/813,317 · Granted Jul 27, 2021

Inventors: Xiaozhou Qian (Shanghai, CN); Xiao Yan Pi (Shanghai, CN); Vipin Tiwari (Dublin, CA)

Assignee: Silicon Storage Technology, Inc.

G11C16/14G11C7/1039G11C7/1045G11C16/28

Abstract

Claims (107)

1. A memory device, comprising:

a memory array that includes pluralities of non-volatile memory cells;

a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells; and

a controller configured to:

erase the pluralities of non-volatile memory cells,

set each of the index memory cells to a first state,

program first data into the memory array by:

reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state,

programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and

setting the first one of the index memory cells to a second state different from the first state;

wherein:

the pluralities of memory cells are arranged in rows and columns that also include the plurality of index memory cells;

all of the non-volatile memory cells in the plurality of non-volatile memory cells associated with the first one of the index memory cells, and the first one of the index memory cells, are located in a single one of the rows;

the pluralities of memory cells are arranged in IO groups, where each of the IO groups includes only one non-volatile memory cell from each of the pluralities of non-volatile memory cells;

for each of the IO groups, some of the non-volatile memory cells in the IO group are located in a first of the rows and others of the non-volatile memory cells in the IO group are located in a second of the rows;

some of the index memory cells are located in the first row, and others of the index memory cells are located in the second row;

for each of the index memory cells located in the first row, the memory device further includes a dummy memory cell that is located in the second row and in a same column that contains the index memory cell; and

for each of the index memory cells located in the second row, the memory device further includes a dummy memory cell that is located in the first row and in a same column that contains the index memory cell.

2. The device of claim 1 , wherein the index memory cells are non-volatile memory cells and wherein the first state is an erased state and the second state is a programmed state.

3. The device of claim 2 , wherein:

the setting of each of the index memory cells to a first state includes erasing each of the index memory cells to the erased state; and

the setting of the first one of the index memory cells to the second state includes programming the first one of the index memory cells to the programmed state.

4. The device of claim 1 , wherein the controller is further configured to:

program second data into the memory array by:

reading the plurality of index memory cells and determining that a second one of the index memory cells is in the first state,

programming the second data into the plurality of the non-volatile memory cells associated with the second one of the index memory cells, and

setting the second one of the index memory cells to the second state.

5. The device of claim 1 , wherein the controller is further configured to:

read the plurality of index memory cells and determine that all of the index memory cells are in the second state, and in response:

erase the pluralities of the non-volatile memory cells, and

set each of the index memory cells to the first state.

6. The device of claim 1 , wherein the controller is further configured to:

program second data into the memory array by:

reading the plurality of index memory cells and determining that all of the index memory cells are in the second state,

erasing the pluralities of the non-volatile memory cells,

setting each of the index memory cells to the first state,

programming the second data into the plurality of the non-volatile memory cells associated with one of the index memory cells, and

setting the associated one of the index memory cells to the second state.

7. The device of claim 1 , wherein the memory array, the plurality of index memory cells and the controller are contained in a single semiconductor chip.

8. A memory device, comprising

a memory array that includes pluralities of non-volatile memory cells;

a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells; and

a controller configured to:

erase the pluralities of non-volatile memory cells,

set each of the index memory cells to a first state,

program first data into the memory array by:

reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state,

programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and

setting the first one of the index memory cells to a second state different from the first state;

wherein:

the pluralities of memory cells are arranged in rows and columns that also include the plurality of index memory cells;

all of the non-volatile memory cells in the plurality of non-volatile memory cells associated with the first one of the index memory cells, and the first one of the index memory cells, are located in a single one of the rows;

the pluralities of memory cells are arranged in TO groups, where each of the IO groups includes only one non-volatile memory cell from each of the pluralities of non-volatile memory cells;

for each of the TO groups, some of the non-volatile memory cells in the TO group are located in a first of the rows and others of the non-volatile memory cells in the TO group are located in a second of the rows;

some of the index memory cells are located in the first row, and others of the index memory cells are located in the second row;

each of the IO groups is located in a plurality of the columns that do not contain any of the other IO groups; and

for any two of the IO groups, at least one of the index memory cells is located in one of the columns that is between the two pluralities of the columns for the two IO groups.

9. A method of operating a memory device that comprises a memory array that includes pluralities of non-volatile memory cells and a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, the method comprising:

erasing the pluralities of non-volatile memory cells,

setting each of the index memory cells to a first state,

programming first data into the memory array by:

reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state,

programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and

setting the first one of the index memory cells to a second state different from the first state;

wherein:

the pluralities of memory cells are arranged in rows and columns that also include the plurality of index memory cells;

all of the non-volatile memory cells in the plurality of non-volatile memory cells associated with the first one of the index memory cells, and the first one of the index memory cells are located in a single one of the rows;

the pluralities of memory cells are arranged in TO groups, where each of the IO groups includes only one non-volatile memory cell from each of the pluralities of non-volatile memory cells;

for each of the TO groups, some of the non-volatile memory cells in the TO group are located in a first of the rows and others of the non-volatile memory cells in the TO group are located in a second of the rows;

some of the index memory cells are located in the first row, and others of the index memory cells are located in the second row;

for each of the index memory cells located in the first row, the memory device further includes a dummy memory cell that is located in the second row and in a same column that contains the index memory cell; and

for each of the index memory cells located in the second row, the memory device further includes a dummy memory cell that is located in the first row and in a same column that contains the index memory cell.

10. The method of claim 9 , the index memory cells are non-volatile memory cells and wherein the first state is an erased state and the second state is a programmed state.

11. The method of claim 10 , wherein:

the setting of each of the index memory cells to a first state includes erasing each of the index memory cells to the erased state; and

the setting of the first one of the index memory cells to the second state includes programming the first one of the index memory cells to the programmed state.

12. The method of claim 9 , further comprising:

programming second data into the memory array by:

reading the plurality of index memory cells and determining that a second one of the index memory cells is in the first state,

programming the second data into the plurality of the non-volatile memory cells associated with the second one of the index memory cells, and

setting the second one of the index memory cells to the second state.

13. The method of claim 9 , further comprising:

reading the plurality of index memory cells and determining that all of the index memory cells are in the second state, and in response:

erasing the pluralities of the non-volatile memory cells, and

setting each of the index memory cells to the first state.

14. The method of claim 9 , further comprising:

programming second data into the memory array by:

reading the plurality of index memory cells and determining that all of the index memory cells are in the second state,

erasing the pluralities of the non-volatile memory cells,

setting each of the index memory cells to the first state,

programming the second data into the plurality of the non-volatile memory cells associated with one of the index memory cells, and

setting the associated one of the index memory cells to the second state.

15. A method of operating a memory device that comprises a memory array that includes pluralities of non-volatile memory cells and a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, the method comprising:

erasing the pluralities of non-volatile memory cells,

setting each of the index memory cells to a first state,

programming first data into the memory array by:

reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state,

programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and

setting the first one of the index memory cells to a second state different from the first state;

wherein:

the pluralities of memory cells are arranged in rows and columns that also include the plurality of index memory cells;

all of the non-volatile memory cells in the plurality of non-volatile memory cells associated with the first one of the index memory cells, and the first one of the index memory cells are located in a single one of the rows;

the pluralities of memory cells are arranged in TO groups, where each of the IO groups includes only one non-volatile memory cell from each of the pluralities of non-volatile memory cells;

for each of the TO groups, some of the non-volatile memory cells in the TO group are located in a first of the rows and others of the non-volatile memory cells in the TO group are located in a second of the rows;

some of the index memory cells are located in the first row, and others of the index memory cells are located in the second row;

each of the TO groups is located in a plurality of the columns that do not contain any of the other TO groups; and

for any two of the TO groups, at least one of the index memory cells is located in one of the columns that is between the two pluralities of the columns for the two IO groups.

Assignments (13)

Priority Claims (1)

Continuity (1)