Semiconductor package and fabricating method thereof
A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
1. A semiconductor package comprising: a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side; a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides; an interposer comprising: a top interposer side; a bottom interposer side; a plurality of lateral interposer sides; and a bottom interposer circuit pattern on the bottom interposer side; a top adhesive that covers the top die side and bonds the top die side to the bottom interposer side; a vertical interconnect comprising: a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and a lateral vertical interconnect surface; and an encapsulating material comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where: the encapsulating material laterally surrounds the semiconductor die, the top adhesive, and the vertical interconnect; and the lateral interposer sides and the lateral substrate sides are free of the encapsulating material; and comprising a dielectric material, different from the encapsulating material, that contacts the lateral vertical interconnect surface, wherein at least a portion of the dielectric material is positioned directly laterally between the semiconductor die and the vertical interconnect.
2. The semiconductor package of claim 1 , wherein the top adhesive covers an entirety of the top die side, and the top adhesive directly contacts the top die side.
3. The semiconductor package of claim 1 , wherein:
the encapsulating material directly contacts the lateral die sides and the vertical interconnect; and
a first lateral encapsulant side of the plurality of lateral encapsulant sides is coplanar with a first lateral substrate side of the plurality of lateral substrate sides.
4. The semiconductor package of claim 1 , wherein the encapsulating material contacts the lateral die sides.
5. The semiconductor package of claim 1 , wherein the encapsulating material, the dielectric material, and the vertical interconnect are directly laterally offset from the top adhesive.
6. The semiconductor package of claim 1 , comprising an underfill material, different from the encapsulating material, between the bottom die side and the top substrate side, and wherein:
the encapsulating material laterally surrounds the underfill material; and
an entirety of each of the lateral encapsulant sides is vertical.
7. The semiconductor package of claim 1 , wherein:
the vertical interconnect comprises an upper part comprising a solderless pillar, and a lower part comprising solder; and
no portion of the encapsulating material is vertically higher than the interposer.
8. The semiconductor package of claim 7 , wherein a boundary between the upper part of the vertical interconnect and the lower part of the vertical interconnect is directly laterally offset from the semiconductor die.
9. A semiconductor package comprising: a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side; a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides; an interposer comprising: a top interposer side; a bottom interposer side; a plurality of lateral interposer sides; and a bottom interposer circuit pattern on the bottom interposer side; a vertical interconnect comprising: a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and a lateral vertical interconnect surface; a dielectric material that contacts and laterally surrounds the vertical interconnect; and an encapsulating material comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where: the encapsulating material laterally surrounds the semiconductor die, and the vertical interconnect; and no portion of the dielectric material is positioned laterally outward from the encapsulating material; and wherein: the dielectric material comprises a lateral side that contacts the encapsulating material; and the lateral interposer sides and the lateral substrate sides are free of the encapsulating material and free of the dielectric material.
10. The semiconductor package of claim 9 , wherein the dielectric material comprises a top side that is coplanar with the top encapsulant side.
11. The semiconductor package of claim 9 , wherein:
the dielectric material comprises a lateral side that is parallel to a respective one of the lateral encapsulant sides, a respective one of the lateral interposer sides, and a respective one of the lateral substrate sides; and
no portion of the dielectric material is positioned directly vertical from the semiconductor die.
12. The semiconductor package of claim 9 , wherein:
a portion of the encapsulating material is positioned directly laterally between the semiconductor die and the dielectric material; and
the dielectric material comprises a laterally outmost side that is entirely vertical.
13. The semiconductor package of claim 9 , comprising a top adhesive that covers the top die side, wherein no portion of the top adhesive is contacted by the dielectric material.
14. The semiconductor package of claim 13 , wherein the encapsulating material, the dielectric layer, and the vertical interconnect are directly laterally offset from the top adhesive.
15. A method of making a semiconductor package, the method comprising: providing a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side; providing a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides; providing an interposer comprising: a top interposer side; a bottom interposer side facing the top encapsulant side; a plurality of lateral interposer sides; and a bottom interposer circuit pattern on the bottom interposer side; providing a top adhesive that covers the top die side and bonds the top die side to the bottom interposer side; providing a vertical interconnect comprising: a top vertical interconnect end that is bonded to the bottom interposer circuit pattern; a bottom vertical interconnect end that is bonded to the top substrate circuit pattern; and a lateral vertical interconnect surface; and providing an encapsulating material comprising a top encapsulant side facing the bottom interposer side, a bottom encapsulant side facing the top substrate side, and a plurality of lateral encapsulant sides, where: the encapsulating material laterally surrounds the semiconductor die, the top adhesive, and the vertical interconnect; and the lateral interposer sides and the lateral substrate sides are free of the encapsulating material; and further comprising providing a dielectric material, different from the encapsulating material, that contacts the lateral vertical interconnect surface, wherein at least a portion of the dielectric material is positioned directly laterally between the semiconductor die and the vertical interconnect.
16. The method of claim 15 , wherein:
the vertical interconnect comprises an upper part comprising a solderless pillar, and a lower part comprising solder; and
no portion of the encapsulating material is vertically higher than the interposer.
17. The method of claim 15 , wherein the encapsulating material, the dielectric material, and the vertical interconnect are directly laterally offset from the top adhesive.