Semiconductor memory device and method of manufacturing the same
According to an embodiment, a semiconductor memory device comprises: a stacked body that includes a plurality of control gate electrodes stacked above a substrate; a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the stacked body; and a source contact that extends in the first direction and is electrically connected to one end of the memory string. Moreover, this source contact is adjacent to the stacked body via a spacer insulating layer. Furthermore, a spacer protective layer including a nitride or a metal oxide is provided between these source contact and spacer insulating layer.
1. A semiconductor memory device comprising:
a plurality of control gate electrodes stacked in a first direction crossing a substrate;
a first semiconductor layer extending in the first direction;
a charge accumulation layer disposed between the control gate electrode and the first semiconductor layer;
a contact extending in the first direction along the plurality of control gate electrodes;
a first spacer insulating layer disposed between the plurality of control gate electrodes and the contact and including a first material; and
a second spacer insulating layer disposed between the contact and the first spacer insulating layer and including a second material different from the first material,
the contact including:
a first portion having a first width in a second direction perpendicular to the first direction;
a second portion having a second width in the second direction; and
an uppermost portion having a third width in the second direction,
the first portion being between the uppermost portion and the second portion,
the third width being larger than the first width,
the first width being the same as the second width.
2. The semiconductor memory device according to claim 1 , wherein
the contact comprises:
a first conductive layer extending in the first direction; and
a barrier metal layer provided between the first conductive layer and the second spacer insulating layer.
3. The semiconductor memory device according to claim 1 ,
the first spacer insulating layer and the second spacer insulating layer including silicon (Si).
4. The semiconductor memory device according to claim 1 further comprising a tunnel insulating layer disposed between the first semiconductor layer and the control gate electrode.
5. The semiconductor memory device according to claim 4 further comprising a block insulating layer disposed between the charge accumulation layer and the control gate electrode.
6. The semiconductor memory device according to claim 5 further comprising:
first inter-layer insulating layers disposed between the control gate electrodes; and
a second inter-layer insulating layer provided above the control gate electrodes and the first inter-layer insulating layers, wherein
the block insulating layer is provided between the second inter-layer insulating layer and the contact.
7. The semiconductor memory device according to claim 5 , wherein
the block insulating layer is divided in the first direction.
8. The semiconductor memory device according to claim 1 comprising:
a second semiconductor layer nearer to the substrate than the plurality of the control gate electrodes.
9. The semiconductor memory device according to claim 8 , wherein
the contact being connected to the second semiconductor layer.
10. The semiconductor memory device according to claim 1 , wherein
the contact being connected to the substrate.
11. The semiconductor memory device according to claim 10 , wherein
the contact extending in a third direction perpendicular to the first direction and the second direction,
the first spacer insulating layer extending in the first direction and the third direction, and
the second spacer insulating layer extending in the first direction and the third direction.
12. The semiconductor memory device according to claim 1 , wherein
the uppermost portion of the contact being directly contacted to the first spacer insulating layer.
13. The semiconductor memory device according to claim 12 , wherein
the first portion and the second portion of the contact being separated from the first spacer insulating layer via the second spacer insulating layer.
14. A semiconductor memory device comprising:
a substrate;
a plurality of control gate electrodes stacked in a first direction crossing the substrate;
a first semiconductor layer extending in the first direction;
a charge accumulation layer disposed between the control gate electrode and the first semiconductor layer;
a contact extending in the first direction along the plurality of control gate electrodes;
a first spacer insulating layer disposed between the plurality of control gate electrodes and the contact and including a first material; and
a second spacer insulating layer disposed between the contact and the first spacer insulating layer and including a second material different from the first material,
the second spacer insulating layer including:
a first portion disposed between the contact and the plurality of control gate electrodes; and
a second portion further from the substrate than the plurality of control gate electrodes, the second portion including an end in the first direction of the second spacer insulating layer, and
a width of the second portion in a second direction perpendicular to the first direction decreasing towards the end in the first direction of the second spacer insulating layer.
15. The semiconductor memory device according to claim 14 , wherein
the contact comprises:
a first conductive layer extending in the first direction; and
a barrier metal layer provided between the first conductive layer and the second spacer insulating layer.
16. The semiconductor memory device according to claim 14 ,
the first spacer insulating layer and the second spacer insulating layer including silicon (Si).
17. The semiconductor memory device according to claim 14 further comprising a tunnel insulating layer disposed between the first semiconductor layer and the control gate electrode.
18. The semiconductor memory device according to claim 17 further comprising a block insulating layer disposed between the charge accumulation layer and the control gate electrode.
19. The semiconductor memory device according to claim 18 further comprising:
first inter-layer insulating layers disposed between the control gate electrodes; and
a second inter-layer insulating layer provided above the control gate electrodes and the first inter-layer insulating layers, wherein
the block insulating layer is provided between the second inter-layer insulating layer and the contact.
20. The semiconductor memory device according to claim 18 , wherein
the block insulating layer is divided in the first direction.
21. The semiconductor memory device according to claim 14 comprising:
a second semiconductor layer nearer to the substrate than the plurality of the control gate electrodes.
22. The semiconductor memory device according to claim 21 , wherein
the contact being connected to the second semiconductor layer.
23. The semiconductor memory device according to claim 14 , wherein
the contact being connected to the substrate.
24. The semiconductor memory device according to claim 23 , wherein
the contact extending in a third direction perpendicular to the first direction and the second direction,
the first spacer insulating layer extending in the first direction and the third direction, and
the second spacer insulating layer extending in the first direction and the third direction.
25. The semiconductor memory device according to claim 14 , wherein
the contact including:
a first portion extending in the first direction; and
a second portion being further from the substrate than the plurality of control gate electrodes,
the first portion being separated from the first spacer insulating layer via the second spacer insulating layer, and
the second portion being directly contacted to the first spacer insulating layer.