IP Library Granted Patent US 11,804,803
Granted Patent B2
US 11,804,803 · App. 16/837,660 · Granted Oct 31, 2023

Techniques for forming integrated inductor-capacitor oscillators and related methods, oscillators, semiconductor devices, systems-on-chips, and other systems

Inventor: Yaojian Leng (Portland, OR)
Assignee: Microchip Technology Incorporated
H03B5/12H01F27/2804H01L21/707H01L27/016H01L28/10H01L28/60H01F2027/2809
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,804,803
App. No.
16/837,660
Granted
Oct 31, 2023
Kind
B2
Abstract

A system-on-chip may include an inductor-capacitor oscillator monolithically integrated into the system-on-chip The inductor-capacitor oscillator may be configured to improve frequency stability and reduce noise when compared to a resistor-capacitor oscillator. Methods of making integrated oscillators may involve forming an inductor at least partially while forming a BEOL structure on a substrate. A capacitor supported on and/or embedded within the semiconductor material of the substrate may be formed before or while forming the BEOL structure. The inductor may be connected to the capacitor in parallel at least partially utilizing the BEOL structure to form an integrated inductor-capacitor oscillator.

Claims (50)

1. A system-on-chip, comprising:

an inductor-capacitor oscillator monolithically integrated into the system-on-chip;

wherein the inductor comprises portions of coils within two adjacent layers supported on a semiconductor substrate of the system-on-chip and overpass regions and underpass regions interconnecting the portions of the coils, the overpass regions located within one of the two adjacent layers, the underpass regions located within another of the two adjacent layers;

wherein at least substantial entireties of the coils of the inductor located outside the overpass regions and the underpass regions comprise a first quantity of electrically conductive material in a first of the two adjacent layers and a second quantity of electrically conductive material in a second of the two adjacent layers, the second quantity of electrically conductive material in direct contact with the first quantity of electrically conductive material, the second quantity of electrically conductive material located outside the overpass regions and the underpass regions comprising a monolithic, contiguous mass of the electrically conductive material partially embedded within a passivation material in the second of the two adjacent layers; and

wherein the overpass regions and the underpass regions interconnecting the portions of the coils comprise the passivation material between the first quantity of electrically conductive material and the second quantity of electrically conductive material, the second quantity of electrically conductive material not being embedded within the passivation material within the overpass regions and the underpass regions.

2. The system-on-chip of claim 1 , wherein at least a portion of a capacitor of the inductor-capacitor oscillator is part of a back-end-of-line (BEOL) structure of the system-on-chip.

3. The system-on-chip of claim 2 , wherein a first plate of the capacitor is located within a first, underlying layer supported on the semiconductor substrate of the system-on-chip, a second plate of the capacitor is located within a second layer supported on the semiconductor substrate of the system-on-chip, and a dielectric material is located between the first plate and the second plate.

4. The system-on-chip of claim 3 , wherein a transition from a surface of the second plate facing the first plate to a lateral side surface of the second plate is rounded.

5. The system-on-chip of claim 3 , wherein the dielectric material extends laterally between the second plate and the first plate and longitudinally along a portion of a periphery of the second plate, such that the dielectric material at least substantially forms a cup shape.

6. The system-on-chip of claim 3 , wherein the second plate is formed as a first bond pad formed in the BEOL structure.

7. The system-on-chip of claim 6 , wherein an electrical connection to the first plate comprises a second bond pad formed in the BEOL structure.

8. The system-on-chip of claim 3 , wherein the second plate comprises a copper or copper alloy material and the first plate comprises an aluminum or aluminum alloy material.

9. The system-on-chip of claim 1 , wherein a capacitor of the inductor-capacitor oscillator is a poly-oxide-poly (POP) capacitor.

10. The system-on-chip of claim 1 , wherein the inductor-capacitor oscillator forms at least a portion of a timing signal generator.

11. The system-on-chip of claim 1 , wherein the inductor-capacitor oscillator is monolithically integrated with other integrated circuitry of the system-on-chip.

12. A method of making an integrated oscillator for a system-on-chip, comprising:

forming an inductor on a semiconductor substrate by forming portions of coils of a first thickness and forming overpass regions and underpass regions of a second, lesser thickness interconnecting the portions of coils, wherein forming the inductor comprises:

supporting the portions of coils of the inductor within two adjacent layers on the semiconductor substrate and interconnecting the portions of coils utilizing the overpass regions and the underpass regions, the overpass regions located within one of the two adjacent layers, the underpass regions located within another of the two adjacent layers;

forming at least substantial entireties of coils of the inductor located outside the overpass regions and the underpass regions to comprise a first quantity of electrically conductive material in a first of the two adjacent layers and a second quantity of electrically conductive material in a second of the two adjacent layers, the second quantity of electrically conductive material in direct contact with the first quantity of electrically conductive material, the second quantity of electrically conductive material located outside the overpass regions and the underpass regions comprising a monolithic, contiguous mass of the electrically conductive material partially embedded within a passivation material in the second of the two adjacent layers; and

forming the overpass regions and the underpass regions interconnecting the portions of coils to comprise the passivation material between the first quantity of electrically conductive material and the second quantity of electrically conductive material, the second quantity of electrically conductive material not being embedded within the passivation material within the overpass regions and the underpass regions;

forming a capacitor supported on and/or embedded within the semiconductor substrate before, or while, forming the inductor; and

connecting the inductor to the capacitor to form integrated monolithically integrated inductor-capacitor oscillator.

13. The method of claim 12 , further comprising trimming a capacitance of the inductor-capacitor oscillator utilizing a bank of capacitors comprising the capacitor.

14. The method of claim 12 , wherein forming the capacitor comprises:

forming a first plate of the capacitor within an uppermost layer of an interconnect on the semiconductor substrate;

placing the passivation material over the first plate;

forming a first hole and a second hole through the passivation material to expose a respective portion of the first plate within each of the first hole and the second hole;

forming a dielectric region of the capacitor by placing a dielectric material within a portion of the first hole, the dielectric material covering the respective portion of the first plate proximate to the first hole; and

forming a second plate of the capacitor and an electrical connection to the first plate by placing another first quantity of an electrically conductive material within a remainder of the first hole in contact with the dielectric material.

15. The method of claim 14 , further comprising forming an electrical connection to the first plate by placing a second quantity of the electrically conductive material within the second hole in contact with the respective portion of the first plate proximate to the second hole.

16. The method of claim 14 , wherein forming the dielectric region comprises:

blanket depositing the dielectric material over a surface of the passivation material located opposite the first plate, over side surfaces of the passivation material defining the first hole and the second hole, and over the respective portions of the first plate within the first hole and the second hole;

placing a protective material within a portion of the first hole over a portion of the dielectric material proximate to the first plate;

removing a remainder of the dielectric material not in contact with the protective material, revealing the passivation material and the respective portion of the first plate within the second hole; and

removing the protective material.

17. The method of claim 16 , wherein placing the first quantity of the electrically conductive material within the remainder of the first hole in contact with the dielectric material comprises rounding a transition from a surface of the second plate facing the first plate to a lateral side surface of the second plate by conforming the first quantity of the electrically conductive material to a shape of the dielectric material within the first hole.

18. A clock module for a microcontroller, comprising:

an inductor-capacitor oscillator monolithically integrated into a substrate comprising a semiconductor material, the inductor-capacitor oscillator comprising:

an inductor supported on the substrate, the inductor comprising portions of coils within two adjacent layers supported on the substrate and overpass regions and underpass regions interconnecting the portions of the coils, the overpass regions located within one of the two adjacent layers, the underpass regions located within another of the two adjacent layers; and

a capacitor operatively connected to the inductor, the capacitor located on the substrate or embedded within the semiconductor material of the substrate,

wherein at least substantial entireties of the coils of the inductor located outside the overpass regions and the underpass regions comprise a first quantity of electrically conductive material in a first of the two adjacent layers and a second quantity of electrically conductive material in a second of the two adjacent layers, the second quantity of electrically conductive material in direct contact with the first quantity of electrically conductive material, the second quantity of electrically conductive material located outside the overpass regions and the underpass regions comprising a monolithic, contiguous mass of the electrically conductive material partially embedded within a passivation material in the second of the two adjacent layers; and

wherein the overpass regions and the underpass regions interconnecting the portions of the coils comprise the passivation material between the first quantity of electrically conductive material and the second quantity of electrically conductive material, the second quantity of electrically conductive material not being embedded within the passivation material within the overpass regions and the underpass regions.

19. An electronic system, comprising:

a microcontroller comprising:

an inductor-capacitor oscillator monolithically integrated into a substrate comprising a semiconductor material, the inductor-capacitor oscillator comprising:

an inductor supported on the substrate, the inductor comprising portions of coils within two adjacent layers supported on the substrate and overpass regions and underpass regions interconnecting the portions of the coils, the overpass regions located within one of the two adjacent layers, the underpass regions located within another of the two adjacent layers; and

a capacitor operatively connected to the inductor, the capacitor located on the substrate or embedded within the semiconductor material of the substrate; and

at least one of an input device, a memory device, an output device, or a sensor device operatively connected to the microcontroller, wherein the microcontroller is configured to transmit control signals to the at least one of the input device, the memory device, the output device, or the sensor device, at least partially utilizing the inductor-capacitor oscillator,

wherein at least substantial entireties of coils of the inductor located outside the overpass regions and the underpass regions comprise a first quantity of electrically conductive material in a first of the two adjacent layers and a second quantity of electrically conductive material in a second of the two adjacent layers, the second quantity of electrically conductive material in direct contact with the first quantity of electrically conductive material, the second quantity of electrically conductive material located outside the overpass regions and the underpass regions comprising a monolithic, contiguous mass of the electrically conductive material partially embedded within a passivation material in the second of the two adjacent layers; and

wherein the overpass regions and underpass regions interconnecting the portions of coils comprise the passivation material between the first quantity of electrically conductive material and the second quantity of electrically conductive material, the second quantity of electrically conductive material not being embedded within the passivation material within the overpass regions and the underpass regions.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2022
From: LENG, YAOJIAN
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 060113/0359 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059263/0001 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 052856/0909 →
Continuity (2)
Provisional Application 62961635 · Jan 15, 2020
Related Publication 20210218365A1 · Jul 15, 2021