IP Library › Granted Patent US 11,003,601
Granted Patent B2
US 11,003,601 · App. 16/837,844 · Granted May 11, 2021

Memory system design using buffer(s) on a mother board

Inventors: Chi-Ming Yeung (Cupertino, CA); Yoshie Nakabayashi (Tokyo, JP); Thomas Giovannini (San Jose, CA); Henry Stracovsky (Portland, OR)
Assignee: Rambus, Inc.
G06F13/1673G06F13/4022G06F13/4068G06F13/4282
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Quick Facts
Patent No.
US 11,003,601
App. No.
16/837,844
Granted
May 11, 2021
Kind
B2
Abstract

A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Claims (37)

1. A mother board comprising:

a first electrical connection to electrically couple a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on the mother board, wherein at least one DIMM in the first set of two or more DIMMs comprises a first internal data buffer coupled to the first primary data buffer via the first electrical connection;

a second electrical connection to electrically couple a second set of two or more DIMMs and a second primary data buffer on the mother board, wherein at least one DIMM in the second set of two or more DIMMs comprises a second internal data buffer coupled to the second primary data buffer via the second electrical connection; and

a third electrical connection to electrically couple a processor to the first primary data buffer and the second primary data buffer in parallel.

2. The mother board of claim 1 , wherein the first electrical connection is coupled in parallel to DIMMs in the first set of two or more DIMMs.

3. The mother board of claim 1 , wherein the second electrical connection is coupled in parallel to DIMMs in the second set of two or more DIMMs.

4. The mother board of claim 1 , wherein the first and second sets of two or more DIMMs comply with a double data-rate (DDR) standard or one of its derivatives.

5. The mother board of claim 1 , further comprising a plurality of I2C buses, each I2C bus coupling the processor to a corresponding DIMM in the first set of two or more DIMMs or the second set of two or more DIMMs and configured for communicating an alert.

6. The mother board of claim 1 , further comprising a plurality of I2C buses, each I2C bus coupling the processor to a corresponding DIMM in the first set of two or more DIMMs or the second set of two or more DIMMs and configured for performing calibration.

7. The mother board of claim 1 , wherein the third electrical connection is part of a BCOM bus.

8. A mother board comprising:

a first electrical connection to electrically couple a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on the mother board, wherein at least one DIMM in the first set of two or more DIMMs comprises a first internal data buffer coupled to the first primary data buffer via the first electrical connection;

a second electrical connection electrically coupling a processor and the first internal data buffer;

a third electrical connection to electrically couple a second set of two or more DIMMs and a second primary data buffer on the mother board, wherein at least one DIMM in the second set of two or more DIMMs comprises a second internal data buffer coupled to the second primary data buffer via the third electrical connection; and

a fourth electrical connection to electrically couple the processor to the first primary data buffer and the second primary data buffer in parallel.

9. The mother board of claim 8 , further comprising: a fifth electrical connection to electrically couple the first primary data buffer to the second primary data buffer, and coupling the first primary data buffer and the second primary data buffer to the processor.

10. The mother board of claim 9 , wherein the fifth electrical connection is part of a BCOM bus.

11. The mother board of claim 8 , wherein the second electrical connection is part of an I2C bus.

12. The mother board of claim 8 , further comprising a sixth electrical connection to electrically couple the processor and a primary registered clock driver (RCD) buffer on the mother board.

13. The mother board of claim 12 , wherein the sixth electrical connection is part of an I2C bus.

14. The mother board of claim 12 , wherein the sixth electrical connection is part of a I2C bus coupled between the processor and the primary RCD buffer for communicating an alert or for performing calibration.

15. The mother board of claim 8 , wherein:

the first electrical connection is coupled in parallel to DIMMs in the first set of two or more DIMMs; and

the second electrical connection is coupled in parallel to DIMMs in the second set of two or more DIMMs.

16. The mother board of claim 8 , wherein the first and second sets of two or more DIMMs comply with a double data-rate (DDR) standard or one of its derivatives.

17. The mother board of claim 8 , wherein the second electrical connection is part of a first I2C bus coupled between the processor and the first set of two or more DIMMs for communicating an alert, and wherein the fourth electrical connection is part of a second I2C bus coupled between the processor and the second set of two or more DIMMs for communicating the alert.

18. The mother board of claim 8 , wherein the second electrical connection is part of a first I2C bus coupled between the processor and the first set of two or more DIMMs for performing calibration, and wherein the fourth electrical connection is part of a second I2C bus coupled between the processor and the second set of two or more DIMMs for performing calibration.

19. A system comprising:

a plurality of memory devices;

a memory controller configured to respond to commands from a command interface to access content stored in one or more of the plurality of memory devices and to perform data operations on content accessed from the plurality of memory devices; and

a mother board comprising:

a first electrical connection to electrically couple a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on the mother board, wherein at least one DIMM in the first set of two or more DIMMs comprises a first internal data buffer coupled to the first primary data buffer via the first electrical connection;

a second electrical connection to electrically couple a second set of two or more DIMMs and a second primary data buffer on the mother board, wherein at least one DIMM in the second set of two or more DIMMs comprises a second internal data buffer coupled to the second primary data buffer via the second electrical connection; and

a third electrical connection to electrically couple a processor to the first primary data buffer and the second primary data buffer in parallel.

20. The system of claim 19 , wherein:

the first electrical connection is coupled in parallel to DIMMs in the first set of two or more DIMMs; and

the second electrical connection is coupled in parallel to DIMMs in the second set of two or more DIMMs.

Continuity (4)
Continuation 16236892 · Dec 31, 2018
Continuation 15071072 · Mar 15, 2016
Provisional Application 62173134 · Jun 9, 2015
Related Publication 20200293468A1 · Sep 17, 2020