Low voltage level shifter for integrated circuit
An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.
1. A level shifter for receiving an input of a first voltage domain and generating an output of a second voltage domain, wherein a “0” in the first voltage domain is a first voltage and a “1” in the first voltage domain is a second voltage and a “0” in the second voltage domain is the first voltage and a “1” in the second voltage domain is a third voltage different than the second voltage, the level shifter comprising:
a first power source providing the third voltage;
a first PMOS transistor comprising a first terminal coupled to the first power source, a gate, and a second terminal;
a second PMOS transistor comprising a first terminal coupled to the first power source, a gate coupled to the second terminal of the first PMOS transistor, and a second terminal coupled to the gate of the first PMOS transistor and to an output node for providing the output;
a first NMOS transistor comprising a first terminal coupled to the second terminal of the first PMOS transistor, a gate configured to receive a first signal; and a second terminal;
a second NMOS transistor comprising a first terminal coupled to the second terminal of the first NMOS transistor, a gate configured to receive the input, and a second terminal coupled to the first voltage;
a third NMOS transistor comprising a first terminal coupled to the output node, a gate coupled to receive a second signal, and a second terminal; and
a fourth NMOS transistor comprising a first terminal coupled to the second terminal of the third NMOS transistor, a gate configured to receive a complement of the input, and a second terminal coupled to the first voltage;
wherein the first signal is twice the second voltage when the input is at the second voltage and is the second voltage when the input is at the first voltage;
wherein the second signal is twice the second voltage when the input is at the first voltage and is the second voltage when the input is at the second voltage; and
wherein when the input is the first voltage, the output is the first voltage, and when the input is the second voltage, the output is the third voltage.
2. The level shifter of claim 1 , further comprising a second power source providing the second voltage.
3. The level shifter of claim 2 , wherein the first signal is generated by a first circuit comprising:
a third PMOS transistor comprising a first terminal coupled to the second power source, a gate, a second terminal, and a bulk; and
a first capacitor comprising a first terminal coupled to the gate of the third PMOS transistor and a second terminal coupled to the second terminal of the third PMOS transistor and the bulk of the third PMOS transistor.
4. The level shifter of claim 3 , wherein the second signal is generated by a second circuit comprising:
a fourth PMOS transistor comprising a first terminal coupled to the second power source, a gate, a second terminal, and a bulk; and
a second capacitor comprising a first terminal coupled to the gate of the fourth PMOS transistor and a second terminal coupled to the second terminal of the fourth PMOS transistor and the bulk of the fourth PMOS transistor.
5. The level shifter of claim 1 , wherein the second voltage is between 0.75 volts and 1.26 volts.
6. The level shifter of claim 2 , wherein the second voltage is between 0.75 volts and 1.26 volts.
7. The level shifter of claim 3 , wherein the second voltage is between 0.75 volts and 1.26 volts.
8. The level shifter of claim 4 , wherein the second voltage is between 0.75 volts and 1.26 volts.