Memory pool allocation for a multi-core system
An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.
1. An apparatus, comprising:
a plurality of processing cores including a first core and a second core;
a pool of memory including a plurality of memory blocks, wherein each memory block includes a data port and a memory check port;
first connections between the first core and each of the plurality of memory blocks;
second connections between the second core and each of the plurality of memory blocks; and,
a chip selection circuit to share access between the first core and the second core to the pool of memory through:
enablement of access of data from the first core to the memory blocks through respective data ports of the memory blocks; and
enablement of access of data from the second core to the memory blocks through respective memory check ports of the memory blocks during assertion of a test enable signal.
2. The apparatus of claim 1 , wherein the chip selection circuit is to share access to the pool of memory between the first core, the second core, and a third core of the plurality of processing cores by enabling access of data from the third core to the memory blocks through the respective memory check ports of the memory blocks.
3. The apparatus of claim 1 , wherein the chip selection circuit is to enable access signals from memory test circuits to the memory blocks through the respective memory check ports of the memory blocks.
4. The apparatus of claim 1 , wherein the chip selection circuit is to enable access of data from the first core through respective data ports and enable access of data from the second core through respective memory check ports based on a determination that the first core is a higher priority core than the second core.
5. The apparatus of claim 1 , wherein the chip selection circuit is to simultaneously:
enable access of data from the first core to a given memory block through a respective data port of the given memory; and
enable access of data from the second core to the given memory block through a respective memory check port of the given memory.
6. The apparatus of claim 1 , wherein the memory blocks are of different sizes.
7. The apparatus of claim 1 , wherein an assignment of memory blocks to respective cores is determined during compilation of software to be executed by the first core and the second core.
8. The apparatus of claim 1 , wherein the chip selection circuit is to:
determine from a compilation process an assignment of memory blocks to cores; and
based on a determination that a given memory block is not assigned to a core, turn off the given memory block.
9. A method, comprising:
using a plurality of processing cores including a first core and a second core;
sharing a pool of memory including a plurality of memory blocks, wherein each memory block includes a data port and a memory check port;
providing first connections between the first core and each of the plurality of memory blocks;
providing second connections between the second core and each of the plurality of memory blocks; and,
sharing access between the first core and the second core to the pool of memory through:
enablement of access of data from the first core to the memory blocks through respective data ports of the memory blocks; and
enablement of access of data from the second core to the memory blocks through respective memory check ports of the memory blocks during assertion of a test enable signal.
10. The method of claim 9 , comprising sharing access to the pool of memory between the first core, the second core, and a third core of the plurality of processing cores by enabling access of data from the third core to the memory blocks through the respective memory check ports of the memory blocks.
11. The method of claim 9 , comprising enabling access signals from memory test circuits to the memory blocks through the respective memory check ports of the memory blocks.
12. The method of claim 9 , comprising enabling access of data from the first core through respective data ports and enable access of data from the second core through respective memory check ports based on a determination that the first core is a higher priority core than the second core.
13. The method of claim 9 , comprising, simultaneously:
enabling access of data from the first core to a given memory block through a respective data port of the given memory; and
enabling access of data from the second core to the given memory block through a respective memory check port of the given memory.
14. The method of claim 9 , wherein the memory blocks are of different sizes.
15. The method of claim 9 , comprising determining an assignment of memory blocks to respective cores during compilation of software to be executed by the first core and the second core.
16. The method of claim 9 , comprising:
determining from a compilation process an assignment of memory blocks to cores; and
based on a determination that a given memory block is not assigned to a core, turning off the given memory block.