3D semiconductor device and structure
A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; a trap-rich layer disposed between the first level and the second level; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the plurality of connection paths includes vertical connections connecting from the first interconnections to the second interconnections, where the third layer includes crystalline silicon, and where the second level is bonded to the first level.
1. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a trap-rich layer disposed between said first level and said second level;
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said plurality of connection paths comprises vertical connections connecting from said first interconnections to said second interconnections,
wherein said third layer comprises crystalline silicon, and
wherein said second level is bonded to said first level; and
a thermally isolative layer disposed between said first level and said second level,
wherein said isolative layer comprises a thermal conductivity less than 0.5 W/m-K.
2. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a trap-rich layer disposed between said first level and said second level;
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said plurality of connection paths comprises vertical connections connecting from said first interconnections to said second interconnections,
wherein said third layer comprises crystalline silicon, and
wherein said second level is bonded to said first level; and
a third level disposed underneath said trap-rich layer,
wherein said third level comprises a memory array.
3. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a trap-rich layer disposed between said first level and said second level; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors,
wherein said plurality of connection paths comprises vertical connections connecting from said first interconnections to said second interconnections,
wherein said third layer comprises crystalline silicon,
wherein said second level is bonded to said first level,
wherein said third layer is a transferred layer,
wherein said transferred layer has been precisely thinned to less than 10 micron, and
wherein said precisely thinned is accomplished with use of a special layer to provide thinning control.
4. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections;
a shielding layer disposed between said first level and said second level; and
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, and
wherein said shielding layer comprises providing protection for said first level from Electro Magnetic Interference (“EMI”) generated from said second level, and
wherein said third layer comprises crystalline silicon.
5. The device according to claim 4 , further comprising:
a trap-rich layer disposed between said second layer and said third layer.
6. The device according to claim 4 , further comprising:
a thermal isolative layer disposed between said first level and said second level,
wherein said isolative layer comprises a thermal conductivity less than 0.5 W/m-K.
7. The device according claim 4 , further comprising:
a third level disposed underneath said shielding layer,
wherein said third level comprises a memory array.
8. The device according claim 4 , further comprising:
a third level disposed underneath said shielding layer,
wherein said third level comprises a first data bus,
wherein said first level comprises a second data bus, and
wherein said first data bus is electrically connected to said second data bus.
9. The device according claim 4 ,
wherein said connections paths comprise vertical connections connecting from said first interconnections to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.
10. The device according claim 4 ,
wherein said third layer is a bonded transferred layer.
11. A 3D semiconductor device, the device comprising:
a first level,
wherein said first level comprises a first layer, said first layer comprising first transistors, and
wherein said first level comprises a second layer, said second layer comprising first interconnections;
a second level overlaying said first level,
wherein said second level comprises a third layer, said third layer comprising second transistors, and
wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections,
a plurality of connection paths,
wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, and
wherein said second level comprises a first data bus,
wherein said first level comprise a second data bus,
wherein said first data bus is electrically connected to said second data bus, and
wherein said third layer comprises crystalline silicon.
12. The device according to claim 11 , the device comprising:
a third level disposed atop said second level,
wherein said third level comprises Radio Frequency (“RF”) circuits and a trap-rich layer.
13. The device according to claim 11 , further comprising:
a thermal isolative layer disposed between said first level and said second level,
wherein said isolative layer has a thermal conductivity less than 0.5 W/m-K.
14. The device according claim 11 , further comprising:
a third level disposed underneath said second level,
wherein said third level comprises a memory array.
15. The device according claim 11 , further comprising:
a third level comprising Radio Frequency (“RF”) circuits and a shielding layer,
wherein said shielding layer provides protection for said second level from Electro Magnetic Interference (“EMI”) generated from said third level.
16. The device according claim 11 ,
wherein said connections paths comprise vertical connections connecting from said first interconnections to said second interconnections, and
wherein said vertical connections comprise through layer vias having a circumscribed diameter of less than 400 nm.