Electronic package with rotated semiconductor die
An electronic package configured to operate at Gigabit-per-second (Gbps) data rates is disclosed. The electronic package includes a package substrate of a rectangular shape. A chip package having a first high-speed interface circuit die is mounted on a top surface of the package substrate. The chip package is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through about 45 degrees. The first high-speed interface circuit die includes a first Serializer/Deserializer (SerDes) circuit block.
1. An electronic package, comprising:
a package substrate of a rectangular shape;
a chip package comprising a first high-speed interface circuit die and a second high-speed interface circuit die in proximity to the first high-speed interface circuit die, wherein the first high-speed interface circuit die and second high-speed interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a molding compound, wherein the chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle; and
a metal ring mounted on the top surface of the package substrate.
2. The electronic package according to claim 1 , wherein the rotation offset angle is between 30 and 75 degrees.
3. The electronic package according to claim 1 , wherein the rotation offset angle is about 45 degrees.
4. The electronic package according to claim 1 , wherein the top surface of the package substrate is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane.
5. The electronic package according to claim 4 , wherein the first high-speed interface circuit die comprises a first edge directly facing a vertex of the package substrate, wherein a first row of input/output (I/O) pads is disposed along the first edge.
6. The electronic package according to claim 5 , wherein the first high-speed interface circuit die comprises a second edge that is perpendicular to the first edge, wherein a second row of input/output (I/O) pads is disposed along the second edge.
7. The electronic package according to claim 6 , wherein a first group of solder balls is arranged along two sides joined at said vertex of the package substrate, and wherein said first row of I/O pads is electrically connected to the first group of solder balls through a plurality first traces, respectively, within one of the four quadrants on the top surface of the package substrate.
8. The electronic package according to claim 7 , wherein a second group of solder balls is arranged along one of said two sides joined at said vertex of the package substrate, and wherein said second row of I/O pads is electrically connected to the second group of solder balls through a plurality second traces, respectively, within said one of the four quadrants on the top surface of the package substrate.
9. The electronic package according to claim 1 , wherein the first high-speed interface circuit die comprises a first Serializer/Deserializer (SerDes) circuit block.
10. The electronic package according to claim 1 , wherein the second high-speed interface circuit die comprises a second Serializer/Deserializer (SerDes) circuit block.
11. The electronic package according to claim 1 , wherein the first high-speed interface circuit die is electrically connected to the second high-speed interface circuit die through the RDL structure.
12. The electronic package according to claim 1 further comprising:
a plurality of capacitors disposed within a triangular region between the metal ring and a side of the rotated chip package.
13. The electronic package according to claim 1 further comprising:
a plurality of chips disposed within a triangular region between the metal ring and a side of the rotated chip package.
14. The electronic package according to claim 13 , wherein the plurality of chips is rotated or non-rotated.
15. The electronic package according to claim 1 , wherein the metal ring comprises an extension portion disposed within a triangular region between the metal ring and a side of the rotated chip package for warpage control.
16. An electronic package, comprising:
a package substrate of a rectangular shape;
a chip package comprising a first high-speed interface circuit die and a second high-speed interface circuit die in proximity to the first high-speed interface circuit die, wherein the first high-speed interface circuit die and second high-speed interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a molding compound, wherein the chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle; and
a metal ring mounted on the top surface of the package substrate.
17. An electronic package, comprising:
a package substrate of a rectangular shape;
a chip package comprising a first high-speed interface circuit die and a second high-speed interface circuit die in proximity to the first high-speed interface circuit die, wherein the first high-speed interface circuit die and second high-speed interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a molding compound, wherein the chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle;
a metal ring mounted on the top surface of the package substrate; and
at least one decoupling capacitor at a corner of the package substrate, wherein the decoupling capacitor is rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle.