Electronic package with rotated semiconductor die
An electronic package includes a base of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the base.
1. An electronic package, comprising:
a base of a rectangular shape;
a chip package comprising a first interface circuit die and a second interface circuit die in proximity to the first interface circuit die, wherein the first interface circuit die and second interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a same molding compound, wherein the chip package is mounted on a top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle; and
a metal ring mounted on the top surface of the base, wherein the metal ring comprises an extension portion completely covering a triangular region between the metal ring and a side of the rotated chip package for warpage control, wherein the extension portion does not overlap with the first interface circuit die or the second interface circuit die.
2. The electronic package according to claim 1 , wherein the rotation offset angle is between 30 and 75 degrees.
3. The electronic package according to claim 1 , wherein the rotation offset angle is about 45 degrees.
4. The electronic package according to claim 1 , wherein the top surface of the base is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane.
5. The electronic package according to claim 4 , wherein the first interface circuit die comprises a first edge directly facing a vertex of the base, wherein a first row of input/output (I/O) pads is disposed along the first edge.
6. The electronic package according to claim 5 , wherein the first interface circuit die comprises a second edge that is perpendicular to the first edge, wherein a second row of input/output (I/O) pads is disposed along the second edge.
7. The electronic package according to claim 6 , wherein a first group of solder balls is arranged along two sides joined at said vertex of the base, and wherein said first row of I/O pads is electrically connected to the first group of solder balls through a plurality first traces, respectively, within one of the four quadrants on the top surface of the base.
8. The electronic package according to claim 7 , wherein a second group of solder balls is arranged along one of said two sides joined at said vertex of the base, and wherein said second row of I/O pads is electrically connected to the second group of solder balls through a plurality second traces, respectively, within said one of the four quadrants on the top surface of the base.
9. The electronic package according to claim 1 , wherein the first interface circuit die comprises a first Serializer/Deserializer (SerDes) circuit block.
10. The electronic package according to claim 1 , wherein the second interface circuit die comprises a second Serializer/Deserializer (SerDes) circuit block.
11. The electronic package according to claim 1 further comprising:
a plurality of capacitors disposed within a triangular region between the metal ring and a side of the rotated chip package.
12. The electronic package according to claim 1 further comprising:
a plurality of chips disposed within a triangular region between the metal ring and a side of the rotated chip package.
13. The electronic package according to claim 12 , wherein the plurality of chips is rotated or non-rotated.
14. An electronic package, comprising:
a base, wherein a top surface of the base is partitioned into four quadrants by two orthogonal axes in a two-dimensional plane;
a chip package comprising a first interface circuit die and a second interface circuit die in proximity to the first interface circuit die, wherein the first interface circuit die and second interface circuit die are mounted on a redistribution layer (RDL) structure and encapsulated within a same molding compound, wherein the chip package is mounted on the top surface of the base and rotated relative to the base above a vertical axis that is orthogonal to the top surface through a rotation offset angle, wherein the first interface circuit die comprises a first edge directly facing a vertex of the base and a second edge that is perpendicular to the first edge, wherein a first row of input/output (I/O) pads is disposed along the first edge and a second row of input/output (I/O) pads is disposed along the second edge;
a first group of solder balls arranged along two sides joined at the vertex of the base, and wherein the first row of I/O pads is electrically connected to the first group of solder balls through a plurality first traces, respectively, within one of the four quadrants on the top surface of the base, wherein the plurality first traces extends in an orthogonal direction;
a second group of solder balls arranged along one of the two sides joined at the vertex of the base, and wherein the second row of I/O pads is electrically connected to the second group of solder balls through a plurality second traces, respectively, within the one of the four quadrants on the top surface of the base; and
a metal ring mounted on the top surface of the base.
15. The electronic package according to claim 14 , wherein the rotation offset angle is between 30 and 75 degrees.
16. The electronic package according to claim 14 , wherein the rotation offset angle is about 45 degrees.