Method for forming semiconductor device that includes covering metal gate with multilayer dielectric

1. A method, comprising:

forming a dummy gate structure over a substrate;

forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;

forming an interlayer dielectric (ILD) layer surrounding the gate spacers;

replacing the dummy gate structure with a metal gate structure;

etching back the metal gate structure to form a gate trench between the gate spacers;

depositing a first dielectric layer in the gate trench, wherein the first dielectric layer has horizontal portions over the metal gate structure and the ILD layer, and vertical portions on sidewalls of the gate spacers;

etching the vertical portions of the first dielectric layer until the sidewalls of the gate spacers are exposed; and

performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner.

2. The method of claim 1 , wherein the first dielectric layer is deposited by a PEALD process, and the first dielectric layer is deposited such that the horizontal portions of the first dielectric layer have a higher etching resistance to an etchant for etching the vertical portions of the first dielectric layer than the vertical portions of the first dielectric layer.

3. The method of claim 1 , wherein performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner is performed until a top surface of a topmost first dielectric layer is higher than a top surface of the ILD layer.

4. The method of claim 1 , further comprising:

depositing a second dielectric layer in the gate trench after performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner, wherein the second dielectric layer extends along the sidewalls of the gate spacers; and

performing a CMP process to the second dielectric layer until a top surface of the ILD layer is exposed.

5. The method of claim 1 , further comprising:

etching back the ILD layer to lower a top surface of the ILD layer prior to etching back the metal gate structure;

forming a hard mask over the etched ILD layer; and

performing a CMP process until a top surface of the metal gate structure is exposed.

6. The method of claim 5 , wherein performing depositing the first dielectric layer and etching the vertical portions of the first dielectric layer in an alternate manner is performed such that a top surface of a topmost first dielectric layer is higher than a bottom surface of the hard mask and lower than a top surface of the hard mask.

7. The method of claim 1 , wherein depositing a first dielectric layer is performed such that the horizontal portions of the first dielectric layer are thicker than the vertical portions of the first dielectric layer.

8. A method, comprising:

etching back a metal gate structure to form a gate trench between gate spacers on opposite sidewalls of the metal gate structure;

forming a first dielectric layer in the gate trench by a first PEALD process, wherein a deposition cycle of the first PEALD process comprises:

exposing the gate trench to a first precursor for a first duration;

providing a directional plasma into the gate trench; and

exposing the gate trench to a second precursor for a second duration;

removing vertical portions of the first dielectric layer to expose sidewalls of the gate spacers; and

forming a second dielectric layer in the gate trench by a second PEALD process, wherein a deposition cycle of the second PEALD process comprises:

exposing the gate trench to the first precursor for a third duration;

providing the directional plasma into the gate trench; and

exposing the gate trench to the second precursor for a fourth duration, wherein the fourth duration is longer than the second duration.

9. The method of claim 8 , wherein forming the second dielectric layer is performed such that the second dielectric layer is in contact with the sidewalls of the gate spacers.

10. The method of claim 9 , wherein forming the second dielectric layer is performed such that the second dielectric layer is separated from top surfaces of the gate spacers at least in part by the first dielectric layer.

11. The method of claim 8 , wherein forming the first dielectric layer and removing vertical portions of the first dielectric layer are defined as a deposition-etch cycle, and the method further comprises performing a plurality of times of the deposition-etch cycle prior to forming the second dielectric layer.

12. The method of claim 11 , wherein the deposition-etch cycle is performed 6 times to 10 times.

13. The method of claim 8 , wherein the first duration is substantially the same as the third duration.

14. The method of claim 8 , wherein removing the vertical portions of the first dielectric layer is performed such that horizontal portions of the first dielectric layer remain over top surfaces of the gate spacers and a top surface of the metal gate structure.

15. A method, comprising:

forming a dummy gate structure over a substrate;

forming a plurality of gate spacers on opposite sidewalls of the dummy gate structure;

forming an interlayer dielectric (ILD) layer surrounding the gate spacers;

etching back the ILD layer to lower a top surface of the ILD layer;

forming a hard mask over the ILD layer;

replacing the dummy gate structure with a metal gate structure;

etching back the metal gate structure to form a gate trench between the gate spacers;

forming a plurality of first dielectric layers over the metal gate structure and the ILD layer, wherein each of the first dielectric layers has a first portion over the metal gate structure and in contact with sidewalls of the gate spacers and a second portion over the ILD layer; and

forming a second dielectric layer over the first dielectric layers, wherein the second dielectric layer extends along sidewalls of the second portions of the first dielectric layers and sidewalls of the gate spacers.

16. The method of claim 15 , wherein forming each of the first dielectric layers comprises:

depositing a dielectric material in the gate trench, wherein the dielectric material has horizontal portions over the metal gate structure and the ILD layer, and vertical portions over the sidewalls of the gate spacers; and

removing the vertical portions of the dielectric material until the sidewalls of the gate spacers are exposed.

17. The method of claim 15 , wherein:

forming the first dielectric layers is performed such that the first dielectric layers are free of seam; and

forming the second dielectric layer is performed such that a seam is formed in the second dielectric layer.

18. The method of claim 17 , wherein a bottom end of the seam of the second dielectric layer is higher than the top surface of the ILD layer.

19. The method of claim 17 , further comprising performing a CMP process to the first dielectric layers and the second dielectric layer until the top surface of the ILD layer is exposed, wherein the seam of the second dielectric layer is removed after the CMP process.

20. The method of claim 15 , further comprising performing a CMP process to the first dielectric layers and the second dielectric layer such that an entirety of the second dielectric layer is removed.