Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same

1. A semiconductor memory device, comprising:

a substrate;

an isolation member defining an active region having a first P-type ion concentration in the substrate;

a gate structure disposed in the substrate;

a first doped region positioned at a first side of the gate structure in the active region;

a second doped region positioned at a second side of the gate structure in the active region;

a bit line positioned on the first doped region;

an air gap positioned adjacent to the bit line;

a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug;

a bit line spacer disposed between the air gap and the barrier layer; and

a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer.

2. The semiconductor device of claim 1 , wherein an upper portion of the barrier layer is disposed between the protruding portion and the second silicide layer.

3. The semiconductor device of claim 2 , wherein a top end of the second silicide layer is higher than a top end of the first silicide layer.

4. The semiconductor device of claim 1 , wherein the first silicide layer and the second silicide layer comprise polysilicon, the first silicide layer comprises tungsten, and the second silicide layer comprises titanium.

5. The semiconductor device of claim 1 , wherein the second silicide layer surrounds the first silicide layer.

6. The semiconductor memory device of claim 1 , wherein the gate structure comprises: a gate dielectric layer conformally disposed on inner sidewalls of a gate trench; and a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

7. The semiconductor memory device of claim 6 , wherein the lower gate electrode includes polysilicon doped with an N-type ion, and the lower gate electrode is conformally disposed on the gate dielectric layer.

8. The semiconductor memory device of claim 6 , further comprising an intermediate gate electrode disposed between the lower gate electrode and the upper gate electrode, wherein the intermediate gate electrode includes a barrier metal, and the intermediate gate electrode is conformally disposed on the lower gate electrode.

9. The semiconductor memory device of claim 6 , wherein the upper gate electrode includes a metal, a metal alloy, or a metal compound, and the upper gate electrode fills the gate trench and has a rail-like shape.

10. The semiconductor memory device of claim 6 , further comprising a capping gate electrode covering an upper surface of the upper gate electrode, wherein the capping gate electrode includes a lower capping gate electrode and an upper capping gate electrode disposed on the lower capping gate electrode, and the lower capping gate electrode includes a barrier metal, and the upper capping gate electrode includes polysilicon doped with an N-type ion.