Dual metal via for contact resistance reduction
A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.
1. A semiconductor device, comprising:
a conductive feature over a substrate;
a ruthenium-containing feature disposed over the conductive feature;
a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature;
a second barrier layer disposed over sidewalls of the first barrier layer; and
a third barrier layer disposed over sidewalls of the second barrier layer, wherein the first, second, and third barrier layers include different material compositions.
2. The semiconductor device of claim 1 , wherein the first barrier layer includes titanium nitride or tantalum nitride.
3. The semiconductor device of claim 1 , wherein the second barrier layer includes titanium nitride and the third barrier layer includes silicon nitride.
4. The semiconductor device of claim 1 , wherein the conductive feature includes titanium nitride.
5. The semiconductor device of claim 1 , wherein the first barrier layer is in physical contact with the conductive feature.
6. The semiconductor device of claim 1 , wherein the first barrier layer interposes the conductive feature and the ruthenium-containing feature and separates the conductive feature from physically contacting the ruthenium-containing feature.
7. The semiconductor device of claim 1 , wherein the third barrier layer interposes the conductive feature and the second barrier layer and separates the conductive feature from physically contacting the second barrier layer.
8. The semiconductor device of claim 1 , wherein the third barrier layer is in physical contact with the first barrier layer.
9. The semiconductor device of claim 1 , further comprising:
a contact etch stop layer disposed over the sidewalls of the ruthenium-containing feature.
10. The semiconductor device of claim 9 , wherein the conductive feature is at least partially embedded in the contact etch stop layer.
11. The semiconductor device of claim 1 , wherein the second barrier layer and the third barrier layer have about a same thickness.
12. A semiconductor device, comprising:
a first cobalt-containing plug disposed over a substrate;
a second cobalt-containing plug disposed over the first cobalt-containing plug;
a first barrier layer containing titanium or tantalum over sidewalls of the second cobalt-containing plug;
a second barrier layer containing silicon over sidewalls of the first barrier layer; and
a dielectric layer surrounding the second barrier layer.
13. The semiconductor device of claim 12 , further comprising:
a conductive cap disposed over and in physical contact with the first cobalt-containing plug.
14. The semiconductor device of claim 12 , wherein a bottom surface of the second cobalt-containing plug is spaced apart from a top surface of the first cobalt-containing plug.
15. The semiconductor device of claim 12 , wherein a total thickness of the first and second barrier layers is greater than a depth of diffusion by cobalt elements from the second cobalt-containing plug into the first and second barrier layers.
16. The semiconductor device of claim 12 , further comprising:
a contact etch stop layer disposed over a lower portion of sidewalls of the second barrier layer.
17. A method, comprising:
providing a structure having a substrate, one or more first dielectric layers over the substrate, a conductive feature embedded in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the conductive feature;
etching a via hole into the one or more second dielectric layers to expose the conductive feature;
depositing a first barrier layer containing silicon into the via hole;
depositing a second barrier layer containing titanium or tantalum into the via hole and over the first barrier layer;
etching the first and second barrier layers in the via hole to expose the conductive feature; and
selectively growing cobalt over the conductive feature.
18. The method of claim 17 , wherein the first barrier layer contains silicon nitride and the second barrier layer contains titanium nitride or tantalum nitride.
19. The method of claim 17 , further comprising:
after the etching of the first and second barrier layers, forming a conductive cap over the conductive feature that is exposed in the via hole.
20. The method of claim 17 , wherein the depositing of the first barrier layer and the depositing of the second barrier layer both include ALD.