IP Library Granted Patent US 11,398,497
Granted Patent B2
US 11,398,497 · App. 16/876,370 · Granted Jul 26, 2022

Three-dimensional memory device containing auxiliary support pillar structures and method of making the same

Inventors: Kengo Kajiwara (Yokkaichi, JP); Atsushi Shimoda (Yokkaichi, JP); Tatsuya Hinoue (Yokkaichi, JP); Junpei Kanazawa (Yokkaichi, JP); Masanori Terahara (Yokkaichi, JP)
Assignee: SANDISK TECHNOLOGIES LLC
H01L27/11582H01L21/76816H01L21/76877H01L23/5226H01L23/5283H01L23/562H01L27/1157H01L27/11519H01L27/11524H01L27/11556H01L27/11565
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Quick Facts
Patent No.
US 11,398,497
App. No.
16/876,370
Granted
Jul 26, 2022
Kind
B2
Abstract

A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

Claims (50)

1. A three-dimensional memory device, comprising:

a first-tier structure located over a substrate and comprising a first alternating stack of first insulating layers and first electrically conductive layers and comprising a first retro-stepped dielectric material portion overlying, and contacting, first stepped surfaces of the first alternating stack;

a second-tier structure located over the first-tier structure and comprising a second alternating stack of second insulating layers and second electrically conductive layers and comprising a second retro-stepped dielectric material portion overlying, and contacting, second stepped surfaces of the second alternating stack;

memory stack structures vertically extending through the first alternating stack and the second alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;

primary support pillar structures, wherein each of the primary support pillar structures vertically extends through the second retro-stepped dielectric material portion, the first alternating stack and the second alternating stack; and

auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack, wherein the auxiliary support pillar structures do not contact the first retro-stepped dielectric material portion.

2. The three-dimensional memory device of claim 1 , wherein top surfaces of the auxiliary support pillar structures contact the bottommost surface of the second alternating stack.

3. The three-dimensional memory device of claim 1 , wherein the auxiliary support pillar structures contact each first insulating layer within the first alternating stack.

4. The three-dimensional memory device of claim 1 , wherein the auxiliary support pillar structures are interlaced with a first subset of the primary support pillar structures that vertically extend through the second stepped surfaces.

5. The three-dimensional memory device of claim 4 , wherein:

a second subset of the primary support pillar structures vertically extend through the first stepped surfaces; and

the first stepped surfaces do not contact any of the auxiliary support pillar structures.

6. The three-dimensional memory device of claim 5 , wherein:

each of the first subset of the primary support pillar structures, the second subset of the primary support pillar structures, and the auxiliary support pillar structures is arranged as a respective periodic two-dimensional array having a same first pitch along a first horizontal direction and having a same second pitch along a second horizontal direction; and

the auxiliary support pillar structures are laterally offset from the first subset of the primary support pillar structures by one half of the second pitch along the second horizontal direction.

7. The three-dimensional memory device of claim 4 , wherein:

the auxiliary support pillar structures are arranged in multiple rows such that each row of the multiple rows is arranged along a second horizontal direction that is perpendicular to the first horizontal direction; and

rows of the first subset of the primary support pillar structures are interlaced with the rows of multiple rows of the auxiliary support pillar structures.

8. The three-dimensional memory device of claim 1 , wherein:

the primary support pillar structures comprise a same set of materials as the memory stack structures; and

the auxiliary support pillar structures comprise an auxiliary fill material that is different from the dielectric materials in the memory film.

9. The three-dimensional memory device of claim 1 , wherein:

the first stepped surfaces continuously extend from a bottommost layer within the first alternating stack to a topmost layer within the first alternating stack and contacts vertical surfaces and horizontal bottom surfaces of the first retro-stepped dielectric material portion; and

the second stepped surfaces continuously extend from a bottommost layer within the second alternating stack to a topmost layer within the second alternating stack and contacts vertical surfaces and horizontal bottom surfaces of the second retro-stepped dielectric material portion.

10. The three-dimensional memory device of claim 1 , further comprising contact via structures vertically extending through the second retro-stepped dielectric material portion and contacting a respective one of the second electrically conductive layers within the second alternating stack, wherein the contact via structures have an areal overlap with a subset of the auxiliary support pillar structures.

11. The three-dimensional memory device of claim 1 , further comprising:

a third-tier structure located over the second-tier structure and comprising a third alternating stack of third insulating layers and third electrically conductive layers and comprising a third retro-stepped dielectric material portion overlying, and contacting, third stepped surfaces of the third alternating stack; and

additional auxiliary support pillar structures;

wherein:

the memory stack structures vertically extend through each layer within the third alternating stack; and

the primary support pillar structures vertically extending through the third retro-stepped dielectric material portion; and

the additional auxiliary support pillar structures vertically extend through the first alternating stack and the second retro-stepped dielectric material portion, underlie the third stepped surfaces, and are located below a horizontal plane including a bottommost surface of the third alternating stack.

12. The three-dimensional memory device of claim 1 , wherein the auxiliary support pillar structures comprise a first dielectric material and the entire primary support pillar structures comprise the first dielectric material.

13. The three-dimensional memory device of claim 1 , wherein:

the auxiliary support pillar structures comprise a first dielectric material;

entire lower portions of the primary support pillar structures comprise the first dielectric material; and

upper portions of the primary support pillars comprise a same set of materials as the memory stack structures.

14. The three-dimensional memory device of claim 1 , wherein each of the primary support pillar structures has a respective top surface located above a horizontal plane including a topmost surface of the second alternating stack.

15. The three-dimensional memory device of claim 14 , wherein each of the auxiliary support pillar structures has a respective top surface located within a horizontal plane including a bottommost surface of the second alternating stack.

16. The three-dimensional memory device of claim 1 , wherein the second subset of the primary support pillar structures vertically extends at least from a top surface of the second retro-stepped dielectric material portion and at least to a bottom surface of the second retro-stepped dielectric material portion.

17. The three-dimensional memory device of claim 1 , wherein the second subset of the primary support pillar structures vertically extends through a respective subset of the first insulating layers and the first electrically conductive layers within the first alternating stack.

18. The three-dimensional memory device of claim 1 , further comprising a source region embedded within a semiconductor material layer in the substrate, wherein:

the semiconductor material layer has a doping of a first conductivity type; and

the source region has a doping of a second conductivity type that is an opposite of the first conductivity type.

19. The three-dimensional memory device of claim 1 , wherein:

each of the auxiliary support pillar structures has a first height; and

each of the primary support pillar structures has a second height that is greater than the first height.

20. The three-dimensional memory device of claim 1 , wherein:

a first subset of the primary support pillar structures does not contact the first retro-stepped dielectric material portion; and

a second subset of the primary support pillar structures directly contacts the first retro-stepped dielectric material portion.

Assignments (4)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2020
From: KAJIWARA, KENGO; SHIMODA, ATSUSHI; HINOUE, TATSUYA; KANAZAWA, JUNPEI; TERAHARA, MASANORI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 052685/0455 →
Continuity (1)
Related Publication 20210358941A1 · Nov 18, 2021
Cited By (6)
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