Semiconductor device and manufacturing method thereof
A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.
1. A method, comprising:
forming a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin has opposite first and second sidewalls and the second semiconductor fin has opposite first and second sidewalls, and the second sidewall of the first semiconductor fin faces the second sidewall of the second semiconductor fin;
forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin;
forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure;
patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin;
forming a dielectric material over the spacer;
after forming the dielectric material over the spacer, forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and
forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.
2. The method of claim 1 , wherein patterning the spacer layer is performed such that a top surface of the first semiconductor fin and a top surface of the second semiconductor fin are free from coverage of the spacer.
3. The method of claim 1 , further comprising etching the spacer such that a topmost surface of the spacer is lower than a top surface of the first semiconductor fin.
4. The method of claim 1 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure is in contact with the spacer.
5. The method of claim 1 , further comprising:
forming a mask layer covering the top surface of the second semiconductor fin prior to forming the first epitaxy structure; and
removing the mask layer after forming the first epitaxy structure.
6. The method of claim 1 , further comprising etching back the dielectric material.
7. A method, comprising:
forming a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin has opposite first and second sidewalls and the second semiconductor fin has opposite first and second sidewalls, and the second sidewall of the first semiconductor fin faces the second sidewall of the second semiconductor fin;
forming a spacer extending from the second sidewall of the first semiconductor fin to the second sidewall of the second semiconductor fin, wherein the first sidewall of the first semiconductor fin and the first sidewall of the second semiconductor fin are free from coverage of the spacer;
forming a mask layer covering a top surface and the first sidewall of the second semiconductor fin, wherein the mask layer is in contact with the spacer;
forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin;
after forming the first epitaxy structure, removing the mask layer to expose the top surface and the first sidewall of the second semiconductor fin; and
forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.
8. The method of claim 7 , further comprising etching the spacer after forming the mask layer and prior to forming the first epitaxy structure.
9. The method of claim 8 , further comprising etching the spacer after forming the forming the first epitaxy structure and prior to forming the second epitaxy structure.
10. The method of claim 7 , wherein forming the spacer comprises:
forming a spacer layer covering the first semiconductor fin and the second semiconductor fin; and
removing portions of the spacer layer from the first sidewall of the first semiconductor fin and the first sidewall of the second semiconductor fin.
11. The method of claim 7 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure is in contact with the second sidewall of the first semiconductor fin.
12. The method of claim 11 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure is in contact with the spacer.
13. The method of claim 7 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure has an asymmetric profile.
14. A method, comprising:
forming a first semiconductor fin and a second semiconductor fin over a substrate, wherein the first semiconductor fin has opposite first and second sidewalls and the second semiconductor fin has opposite first and second sidewalls, and the second sidewall of the first semiconductor fin faces the second sidewall of the second semiconductor fin;
forming a spacer extending from the second sidewall of the first semiconductor fin to the second sidewall of the second semiconductor fin, wherein the first sidewall of the first semiconductor fin and the first sidewall of the second semiconductor fin are free from coverage of the spacer;
forming a dielectric layer over the spacer and between the first semiconductor fin and the second semiconductor fin;
forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and
forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.
15. The method of claim 14 , further comprising etching the dielectric layer such that a top surface of the dielectric layer is lower than a top surface of a first end of the spacer.
16. The method of claim 15 , further comprising, after etching the dielectric layer, etching the first end of the spacer such that the top surface of the first end of the spacer is lower than the top surface of the dielectric layer.
17. The method of claim 14 , further comprising etching the dielectric layer such that a top surface of the dielectric layer is lower than a top surface of the first semiconductor fin.
18. The method of claim 14 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure is separated from the dielectric layer.
19. The method of claim 14 , wherein forming the first epitaxy structure is performed such that the first epitaxy structure is in contact with the second sidewall of the first semiconductor fin.
20. The method of claim 1 , further comprising forming an interlayer dielectric covering the first epitaxy structure and the second epitaxy structure.