Ratiometric gain error calibration schemes for delta-sigma ADCs with programmable gain amplifier input stages
An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.
1. An analog to digital converter (ADC), comprising:
an ADC voltage input terminal;
an ADC reference input terminal;
a buffer circuit including:
a buffer voltage input terminal;
a buffer voltage output terminal; and
a variable resistor including a plurality of resistive branches connected to each other in parallel, wherein each resistive branch is individually selectable;
a multiplexer connected between the ADC voltage input terminal and the buffer voltage input terminal and between the ADC reference input terminal and the buffer voltage input terminal; and
control logic configured to, in a calibration phase:
cause the multiplexer to route the ADC reference input terminal to the buffer voltage input terminal;
determine a given gain value of the ADC for which gain error is to be calibrated;
determine a set of the plurality of resistive branches in the buffer circuit to be used to achieve the given gain value;
successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled;
determine an output code resulting after enabling all resistive branches of the set; and
from the output code, determine a gain error of the given gain value of the ADC;
wherein the control logic is further configured to take corrective action based upon the gain error of the given gain value of the ADC.
2. The ADC of claim 1 , wherein each resistive branch of the variable resistor includes an individual pair of resistors matched to each other and to feedback resistors of the buffer circuit.
3. The ADC of claim 1 , wherein the control logic is further configured to, while successively enabling a given different resistive branch of the variable resistor of the set, disable all other resistive branches of the variable resistor.
4. The ADC of claim 3 , wherein the control logic is further configured to, in a normal operation mode, enable the given gain value by enabling the resistive branches of the set.
5. The ADC of claim 1 , further comprising a sampling circuit configured to:
sample output of the buffer circuit;
selectively apply a gain to the output of the buffer circuit; and
provide the sampled output of the buffer circuit with the applied gain to an integrator circuit.
6. The ADC of claim 5 , wherein the sampled output of the buffer circuit with the applied gain has an effective gain of one with respect to voltage on the ADC reference input terminal as received by the buffer circuit.
7. The ADC of claim 1 , wherein:
the given gain value of the ADC is an integer G; and
a size of the set is G−1.
8. The ADC of claim 7 , further comprising a sampling circuit, wherein:
each resistive branch of the set is enabled for a same number of samples to be sampled by the sampling circuit over a conversion period;
the sampling circuit is configured to sample for a duration of (G−1) conversion periods corresponding to enablement of each resistive branch of the set;
the sampling circuit is further configured to sample for an additional conversion period corresponding to disablement of all of the resistive branches of the variable resistor; and
the control logic is further configured to determine the gain error from an average of the samples from each of the (G−1) and the additional conversion periods.
9. The ADC of claim 1 , wherein:
the given gain value of the ADC is an integer G;
each resistive branch of the set is enabled for a same number of samples to be sampled by the sampling circuit over a conversion period, resulting in a total number of samples; and
the same number of samples is equal to the total number of samples divided by the given gain value of the ADC.
10. The ADC of claim 9 , wherein a quotient of the total number of samples divided by the given gain value of the ADC has no remainders.
11. The ADC of claim 10 , wherein:
the given gain value is a multiple of 2; and
the ADC includes an add and shift circuit to realize an average value of charge.
12. A method, comprising, during a calibration phase of an analog to digital converter (ADC):
routing an ADC reference input terminal of the ADC to a buffer voltage input terminal of a buffer circuit of the ADC;
determining a given gain value of the ADC for which gain error is to be calibrated;
determining a set of a plurality of resistive branches of a variable resistor in the buffer circuit to be used to achieve the given gain value, the resistive branches connected to each other in parallel and individually selectable;
successively enabling a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled;
determining an output code resulting after enabling all resistive branches of the set; and
from the output code, determining a gain error of the given gain value of the ADC;
taking corrective action based upon the gain error of the given gain value of the ADC;
wherein the method further comprises, during a normal phase of the ADC, apply the corrective action determined during the calibration phase.
13. The method of claim 12 , wherein each resistive branch of the variable resistor includes an individual pair of resistors matched to each other and to feedback resistors of the buffer circuit.
14. The method of claim 12 , further comprising, while successively enabling a given different resistive branch of the variable resistor of the set, disabling all other resistive branches of the variable resistor.
15. The method of claim 14 , further comprising, in a normal operation mode, enabling the given gain value by enabling the resistive branches of the set.
16. The method of claim 12 , further comprising, with a sampling circuit:
sampling output of the buffer circuit;
selectively applying a gain to the output of the buffer circuit; and
providing the sampled output of the buffer circuit with the applied gain to an integrator circuit.
17. The method of claim 16 , wherein the sampled output of the buffer circuit with the applied gain has an effective gain of one with respect to voltage on the ADC reference input terminal as received by the buffer circuit.
18. The method of claim 12 , wherein:
the given gain value of the ADC is an integer G; and
a size of the set is G−1.
19. The method of claim 18 , further comprising:
enabling each resistive branch of the set for a same number of samples to be sampled over a conversion period;
sampling for a duration of (G−1) conversion periods corresponding to enablement of each resistive branch of the set;
sampling for an additional conversion period corresponding to disablement of all of the resistive branches of the variable resistor; and
determining the gain error from an average of the samples from each of the (G- 1 ) and the additional conversion periods.
20. The method of claim 12 , wherein:
the given gain value of the ADC is an integer G;
the method includes enabling each resistive branch of the set for a same number of samples to be sampled by the sampling circuit over a conversion period, resulting in a total number of samples; and
the same number of samples is equal to the total number of samples divided by the given gain value of the ADC.