Semiconductor integrated circuit device
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.
1. A semiconductor integrated circuit device comprising
a circuit block having first and second cell rows each having a plurality of cells arranged in a first direction, the first and second cell rows being arranged in a second direction perpendicular to the first direction, wherein
the first cell row includes a first cell-row-terminating cell that does not contribute to a logical function of the circuit block at a first end thereof, and the second row includes a second cell-row-terminating cell that does not contribute to a logical function of the circuit block at a second end thereof, the first end of the first cell row and the second end of the second cell row being at the same position in the first direction,
a first cell is adjacent to the first cell-row-terminating cell in the first direction, and a second cell is adjacent to the second cell-row-terminating cell in the first direction,
the first and second cell-row-terminating cells each include:
a plurality of fins extending in the first direction; and
a plurality of gate structures extending in the second direction and including a first gate structure placed at a cell end on an inner side of the circuit block, and
the first and second cells each include:
a plurality of fins extending in the first direction, the plurality of fins of the first cell facing the plurality of fins of the first cell-row-terminating cells, respectively, and the plurality of fins of the second cell facing the plurality of fins of the second cell-row-terminating cells, respectively,
the first and second cell-row-terminating cells have cell width different from each other, the cell width being a cell dimension in the first direction.
2. The semiconductor integrated device of claim 1 , wherein
a first distance in the first direction between the plurality of fins of the first cell-row terminating cell and the plurality of fins of the first cell is the same as a second distance in the first direction between the plurality of fins of the second cell-row terminating cell and the plurality of fins of the second cell.
3. The semiconductor integrated device of claim 1 , wherein
end of the plurality of fins on the inner side of the circuit block of the first and second cell-row-terminating cells do not overlap with the first gate structure in a plan view.
4. The semiconductor integrated device of claim 3 , wherein
end of the plurality of fins on an outer side of the circuit block of the first and second cell-row-terminating cells overlap with any one of the gate structures other than the first gate structure in a plan view.
5. The semiconductor integrated device of claim 4 , wherein
the any one of the gate structures is a second gate structure placed at a cell end on the outer side of the circuit block.
6. The semiconductor integrated device of claim 1 , wherein
end of the plurality of fins on an outer side of the circuit block of the first and second cell-row-terminating cells overlap with any one of the gate structures other than the first gate structure in a plan view.
7. The semiconductor integrated device of claim 6 , wherein
the any one of the gate structures is a second gate structure placed at a cell end on the outer side of the circuit block.
8. A semiconductor integrated circuit device comprising
a circuit block having first and second cell rows each having a plurality of cells arranged in a first direction, the first and second cell rows being arranged in a second direction perpendicular to the first direction, wherein
the first cell row includes a first cell-row-terminating cell that does not contribute to a logical function of the circuit block at a first end thereof, and the second row includes a second cell-row-terminating cell that does not contribute to a logical function of the circuit block at a second end thereof, the first end of the first cell row and the second end of the second cell row being at the same position in the first direction,
a first cell is adjacent to the first cell-row-terminating cell in the first direction, and a second cell is adjacent to the second cell-row-terminating cell in the first direction,
the first and second cell-row-terminating cells each include:
a plurality of fins extending in the first direction; and
a plurality of gate structures extending in the second direction and including a first gate structure placed at a cell end on an inner side of the circuit block, and a second gate structure adjacent to the first gate structure in the first direction, and
the first and second cells each include:
a plurality of fins extending in the first direction, the plurality of fins of the first cell facing the plurality of fins of the first cell-row-terminating cells, respectively, and the plurality of fins of the second cell facing the plurality of fins of the second cell-row-terminating cells, respectively, and
a third gate structure adjacent to the first gate structure in the first direction,
the first and second cell-row-terminating cells have cell width different from each other, the cell width being a cell dimension in the first direction,
the plurality of fins of the first and second cell-row-terminating cells are at least partly between the first gate structure and the second gate structure,
the plurality of fins of the first and second cells are at least partly between the first gate structure and the third gate structure.
9. The semiconductor integrated device of claim 8 , wherein
a first distance in the first direction between the plurality of fins of the first cell-row terminating cell and the plurality of fins of the first cell is the same as a second distance in the first direction between the plurality of fins of the second cell-row terminating cell and the plurality of fins of the second cell.
10. The semiconductor integrated device of claim 8 , wherein
end of the plurality of fins on an outer side of the circuit block of the first and second cell-row-terminating cells overlap with any one of the gate structures other than the first gate structure in a plan view.
11. The semiconductor integrated device of claim 10 , wherein
the any one of the gate structures is a fourth gate structure placed at a cell end on the outer side of the circuit block.